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SAA7785 ThunderBird AvengerTM PCI Audio Accelerator
Preliminary specification 1999 Nov 12
Philips Semiconductors
Philips Semiconductors
Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
SAA7785
IEEE 1394 devices via 14 Channel Virtual Write Master * Superior hardware acceleration for minimum CPU consumption * Broadest API compatibility including DirectSound3DTM , EAXTM , and A3DTM * 64 hardware wavetable polyphony
GENERAL DESCRIPTION
The SAA7785 ThunderBird AvengerTM is a high-performance PCI audio accelerator offering the ultimate home theater, gaming and music solution. Armed with QSound's advanced QMSSTM , ThunderBird AvengerTM transforms ordinary stereo games, movies and music to 5.1 speaker output. An integrated S/PDIF OUT connects to consumer audio equipment and S/PDIF IN support provides digital connection from a CD player or other digital audio equipment. The ThunderBird AvengerTM supports redirection of up to 5.1 streams from PCI to USB or IEEE 1394 devices. Full hardware acceleration of DirectSoundTM , 3D audio, music synthesis and gameport functions provides increased graphic framerates and industry leading low CPU consumption. Utilizing a specialized DSP controller and combining with a AC97 codec creates a high quality, high performance, low cost audio subsystem.
* Professional soft-synth with 256 voice polyphony and XG support * Second generation ActiMedia programmable DSP architecture * Global reverb for external digital and analog input sources * Enhanced MIDI reverb and chorus (per track and global) * Independent I2S input and output ports * Comprehensive Real Mode DOS and DOS windows support * Dual gameport accelerator with leagacy and digital joystick modes * PC/PCI, DDMA, and LAMTM PCI DMA support * Supports quad and dual AC97 CODECS
FEATURES
* 2, 4, or 5.1 speaker and headphone 3D algorithms * QSound3DInteractive TM interactive positional 3D * QSound Multi-Speaker System TM stereo to quad or stereo to 5.1 processing * QSound Environmental ModelingTM (I3D Level 2.0, EAXTM 1.0/2.0 compatible) * QXpanderTM and stereo-to-3D remapping * Integrated S/PDIF OUT and optional S/PDIF IN * AC3 5.1 or stereo playback through S/PDIF output * Processing up to 512 simultaneous inputs including 256 DirectSound streams and up to 96 concurrent CD quality 3D streams * Redirection up to 5.1 streams from PCI to USB or
* 3.3 v operation with 5 v tolerant I/O * Windows(R) 95 , Windows(R) 98, and Windows(R) 2000 (WDM) drivers
APPLICATIONS
* Complete audio subsystem when combined with AC97 CODEC * PC sound cards and motherboards * Video games and other PCI bus-based multimedia applications
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Philips Semiconductors
Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator ORDERING INFORMATION
TYPE NUMBER SAA7785 SAA7785 NAME TQFP128 TQFP100 PACKAGE DESCRIPTION Thin quad flat pack; 128 leads (lead length 1.00 mm); body 14 x 14 x 1.00 mm Thin quad flat pack; 100 leads (lead length 1.00 mm); body 14 x 14 x 1.00 mm
SAA7785
VERSION 25-90040 25-90042
QUICK REFERENCE DATA
Condition Ambient Operating Temperature Ambient Storage Temperature Non-Operating Core and Ring Supply Voltage Operating Core Supply Voltage Operating Ring Supply Voltage 5V Tolerant Supply (5.0V nominal supply) NWELL to VDD Differential 3V Tolerant I/O DC Input Voltage 3V Tolerant I/O DC Output Voltage 5V Tolerant I/O DC Input Voltage 5V Tolerant I/O DC Output Voltage DC Input Current (at VI < 0V or VI > VDD) DC Output Current (at VO < 0V or VO > VDD) Power Dissipation TA TS VDD, VDDIC VDDIC VDD NWELL NWELL-VDD VI3 VO3 VI5 VO5 II IO PD Symbol Maximum Ratings 0C to +70C -65C to +150C -0.5V to 4.6V * -0.5V to 3.63V * 3.0V to 3.63V * -0.5V to 5.5V * 0 (NWELL-VDD) < 4.0V -0.5V to VDD+0.5V ( 4.6V max)+ -0.5V to VDD+0.5V ( 4.6V max)+ -0.5V to 5.5V ( 6.0V max)+ -0.5V to VDD+0.5V ( 4.6V max)+ 20mA 20mA 500mW
*Refer to Section 3.1 to ensure proper power supply sequencing as well as voltage ranges. +Items in parenthesis are non-operating conditions.
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Philips Semiconductors
Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
FIGURE 1 BLOCK DIAGRAM
AC Link Interface I 2S Interface S/P DIF Output DSP Interrupt Controller INTRs
SAA7785
I2S Port S/P DIF
AC LINK
Serial CFG Port
PCI Configuration Headers DSP DATA BUS
PCI Bus Test Port
PCI Master/Slave Interface
Legacy DMA Interface
DSP Core
INTA#
Serial Interrupt Controller
GPIO
General Purpose I/O
OPL3 Registers
DSP Code RAM
GamePort
Game Port Interface
Sample Fetch Accelerator DSP Memory Controller Virtual Registers DSP Data RAM
PLL Test Logic
AC97 Xtal_out
PLL Cell
Multimedia Timer
Address Generation
FM Accelerator Prog IIR Filter
Host/DSP Interface MIDI Regs and UART
Phase/Env Accelerator
MIDI Interface
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DSP CODE BUS
SoundBlaster Registers
DSP Code ROM
Philips Semiconductors
Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator PINNING
TABLE 1 Signal and Pin Names for 128 pin SAA7785 ThunderBird AvengerTM
SAA7785
PIN #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PIN NAME BIT_CLK SDATA_OUT SDATA_IN0 SDATA_IN1 AC_RST# VSS JAB1 JBB1 VDD JACX JBCX MIDIOUT JBCY NWELL2 JACY VSSIC JBB2 TRI#/CFGCLK MIDIIN VDD VSS TRI#/CFGCLK NAND#/CFGDAT SPDO CCLK DSPCLK SPDI VDD VSS PSUB PLLAPWR PLLAGND 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 GNT# PME# RST# VSS PCLK PCGNT# PCREQ# VDD GNT# VDDIC REQ# PGPIO0 AD13 AD30 VDD PGPIO1 AD29 VSS NWELL0 PGPIO2 AD28 VSSIC AD27 VDD AD26 VSS AD25 AD24 C/BE3# IDSEL AD23 PGPIO3 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 AD22 VDD AD21 AD20 AD19 VSS AD18 AD17 AD16 PGPIO7 NWELL3 VSS C/BE2# FRAME# VDD IRDY# PGPIO6 VDDIC TRDY# VSS DEVSEL# STOP# PGPIO5 VDD PERR# SERR# PAR C/BE1 AD15 AD14 VSS AD13 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 AD12 AD11 AD10 NWELL1 PGPIO4 AD9 VDD AD8 VSS C/BE0 VDDIC AD7 VDD AD6 AD5 VSS AD4 AD3 AD2 VSSIC AD1 AD0 VDD TWS TSD TSCK CLKRUN RESVDS RSD/GPIO2 RSCK/GPIO1 RWS/GPIO0 SYNC
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Philips Semiconductors
Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
SAA7785
FIGURE 2
PIN CONFIGURATION
SAA7785 ThunderBird AvengerTM PINS ON 128 PIN TQFP PACKAGE DIAGRAM (TOP VIEW).
SYNC RWS/DGPIO0 RSCK/DGPIO1 RSD/DGPIO2 RESVD CLKRUN# TSCK TSD TWS VDD AD0 AD1 VSSIC AD2 AD3 AD4 VSS AD5 AD6 VDD AD7 VDDIC C/BE0# VSS AD8 VDD AD9 PGPIO4 NWELL AD10 AD11 AD12 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97
1999 Nov 12
INTA# PME# RST# VSS PCLK PCGNT# PCREQ# VDD GNT# VDDIC REQ# PGPIO0 AD31 AD30 VDD PGPIO1 AD29 VSS NWELL PGPIO2 AD28 VSSIC AD27 VDD AD26 VSS AD25 AD24 C/BE3# IDSEL AD23 PGPIO3
Notes: 1. Package body size is 14 mm. 2. Scale is approx 1" = 5.08 mm (5X actual size). 3. Use package bond form nuber 23-xxxxx.
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
BIT_CLK SDATA_OUT SDATA_IN0 SDATA_IN1 AC_RST# VSS JAB1 JBB1 VDD JACX JBCX MIDIOUT JBCY NWELL JACY VSSIC JBB2 JAB2 MIDIIN VDD VSS TRI#/CFGCLK NAND#/CFGDAT SPDO CCLK DSPCLK SPDI VDD VSS PSUB PLLAPWR PLLAGND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
SAA7785
128 PIN TQFP
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
AD13 VSS AD14 AD15 C/BE1# PAR SERR# PERR# VDD PGPIO5 STOP# DEVSEL# VSS TRDY# VDDIC PGPIO6 IRDY# VDD FRAME# C/BE2# VSS NWELL PGPIO7 AD16 AD17 AD18 VSS AD19 AD20 AD21 VDD AD22
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Philips Semiconductors
Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator PINNING
TABLE 2 PIN #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
SAA7785
PIN DEFINITIONS FOR THE 100 Pin SAA7785 ThunderBird AvengerTM
PIN NAME
BIT_CLK SDATA_OUT SDATA_IN AC_RST# VSS JAB1 JBB1 JACX JBCX MIDIOUT JBCY JACY VSSIC JBB2 JAB2 MIDIIN VDD TRI#/CFGCLK NAND#/CFGDAT SPDO CCLK DSPCLK PSUB PLLAPWR PLLAGND INTA# PME# RST# VSS
30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58
PCLK PCGNT# PCREQ# GNT# VDDIC REQ# AD31 AD30 VDD AD29 NWELL_40 AD28 VSSIC AD27 AD26 VSS AD25 AD24 C/BE3# IDSEL AD23 AD22 VDD AD21 AD20 AD19 AD18 AD17 AD16
59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
VSS C/BE2# FRAME# IRDY# VDDIC TRDY# DEVSEL# STOP# VDD PERR# SERR# PAR C/BE1# AD15 AD14 VSS AD13 AD12 AD11 AD10 NWELL1 AD9 VDD AD8 C/BE0# VDDIC AD7 AD6
87 88 89 90 91 92 93 94 95 96 97 98 99 100
AD5 VSS AD4 AD3 AD2 VSSIC AD1 AD0 VDD CLKRUN# RSD/GPIO2 RSCK/GPIO1 RWS/GPIO0 SYNC
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Philips Semiconductors
Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
SAA7785
SAA7785 ThunderBird AvengerTM pinout for 100 pin package
SYNC RWS/DGPIO0 RSCK/DGPIO1 RSD/DGPIO2 CLKRUN# VDD AD0 AD1 VSSIC AD2 AD3 AD4 VSS AD5 AD6 AD7 VDDIC C/BE0# AD8 VDD AD9 NWELL AD10 AD11 AD12 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1999 Nov 12
INTA# PME# RST# VSS PCLK PCGNT# PCREQ# GNT# VDDIC REQ# AD31 AD30 VDD AD29 NWELL AD28 VSSIC AD27 AD26 VSS AD25 AD24 C/BE3# IDSEL AD23
Notes: 1. Package body size is 14 mm. 2. Scale is approx 1" = 5.08 mm (5X actual size). 3. Use package bond form nuber 23-61269.
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
BIT_CLK SDATA_OUT SDATA_IN0 AC_RST# VSS JAB1 JBB1 JACX JBCX MIDIOUT JBCY JACY VSSIC JBB2 JAB2 MIDIIN VDD TRI#/CFGCLK NAND#/CFGDAT SPDO CCLK DSPCLK PSUB PLLAPWR PLLAGND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
SAA7785
100 PIN TQFP
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
AD13 VSS AD14 AD15 C/BE1# PAR SERR# PERR# VDD STOP# DEVSEL# TRDY# VDDIC IRDY# FRAME# C/BE2# VSS AD16 AD17 AD18 AD19 AD20 AD21 VDD AD22
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Philips Semiconductors
Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
SAA7785
FUNCTIONAL OVERVIEW
QSound 3D Audio Algorithms QSound Labs most advanced algorithms for 3D virtualization, multichannel processing, audio mixing and wavetable synthesis result in unsurpassed 3D audio. QSound's Q3DTM is the only solution developed natively for speakers and therefore requires no crosstalk cancellation. The result is a wide "sweetspot", strong positional perception and insensitivity to head movement and position. Listeners can enjoy a true 3D experience with only two speakers connected to their PC. QSound Multi-Speaker SystemTM (QMSSTM ) uses a proprietary stereo-to-quad or 5.1 remapping algorithm to transform ordinary stereo into more immersive quad and 5.1 outputs. Not simply mirroring the front speaker output to the rear speakers, QMSSTM creates 4 and 5.1 individual channels. The result is DirectSound games become more realistic with action all around the listener; music CD, MP3 and MIDI playback become more immersive; and stereo and Dolby ProLogic film clips become theatre-like in presentation without needing a specific decoder. QSound3DInteractiveTM utilizes the ActiMediaTM DSP to interactively position DirectSound streams in 3D space around the listener. Four different 3D engines, based on HRTF and patented QSound technology, render sound over headphones, 2, 4 or 5.1 speakers. Q3DITM uses the industry standard DirectSound3DTM API and is compatible with DirectSound, EAXTM, and A3D1.0TM applications. QSound Environmental ModelingTM (QEMTM ) adds further realism by adding reverb, occulsion and obstruction as additional positional ques. With QEM enabled, each DirectSound3D sound source receives reverb simulating acoustic reflections based on the regions reverb present and the sources' current position relative to the listener. In addition obstruction and occlusion filters are used to simulate the acoustical effects of barriers and openings in a games virtual 3D environment such as walls, doorways and pillars, and is compliant with I3D Level 2.0. S/PDIF OUT/IN The SAA7785 ThunderBird AvengerTM provides an integrated S/PDIF OUT port enabling users to output 1999 Nov 12 9
AC3 data from a DVD directly to an AC3 decoder. The S/PDIF stereo output capability allows users to connect to a variety of consumer audio equipment, such as a stereo receiver, minidisk, or digital speakers. S/PDIF IN support through the I 2S port enables digital connection from a CD player or other audio equipment that utilizes the S/PDIF format. Superior Concurrency The SAA7785 ThunderBird AvengerTM combines its 64 hardware input buffers with software (256 MIDI channels and 192 DirectSoundTM inputs) for a total of 512 simultaneous streams. The ThunderBird AvengerTM can process 64 combined audio and wavetable voices in hardware plus an additional 192 audio streams using QSound's efficient MMX host engine. In addition, Avenger offers game developers up to 96 simultaneous 3D streams. For greater concurrency and higher music polyphony a professional quality 256 voice soft-synth is available. This can be used for all music synthesis reserving all 256 streams for other audio sources, making the ThunderBird Avenger TM an excellent solution for gaming applications. Hardware Acceleration The SSA7785 ThunderBird AvengerTM is a true hardware audio accelerator. CPU consumption is minimized by processing sample rate conversion, panning, mixing, 3D virtualization, filtering, music synthesis, multichannel conversion, and gameport functions in the hardware DSP. This frees up the host CPU to perform other tasks, boosting graphic frame rates and raising system benchmarks. 320 Voice CD Quality Wavetable Synthesis ThunderBird Avenger TM includes two wavetable synthesis engines. When hardware mode is enabled, the ActiMediaTM DSP can produce up to 64 wavetable 44Khz, 16 bit voices. This mode minimizes CPU consumption and is ideal for games with MIDI music tracks. In addition, a professional quality soft-synth can produce up to 256 voices including special effects. The soft-synth is configurable and can be optimized for highest quality with pure music applications or for minimum CPU consumption in gaming applications. Combining both hardware and software synthesizers allows for 320
Philips Semiconductors
Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
SAA7785
total simultaneous voices. ActiMediaTM DSP Architecture ActiMediaTM DSP architecture combines the strengths of programmable and fixed function DSP architectures. Programmability enables custom features, field upgrades, and simple application development, while an array of gate-efficient fixed function DSP processors (accelerators) operate in parallel to provide an excellent price/performance ratio. Unlike fixed-point DSPs that must use a single resolution for all audio processing, each accelerator is designed with the optimum resolution for its function. This provides audio integrity without the cost of high resolution or floating point programmable DSP implementation. Digital Model Dual Game Port The software polling used by analog game ports can consume up to 10% of the host CPU. ThunderBird PCI products utilize a digital operation mode that can eliminate software polling and accelerate the game port function resulting in significantly improved system performance. Joystick buttons can be polled or interrupt driven to further enhance performance. A default analog mode assures compatibility with DOS and other non-DirectInputTM applications. Comprehensive Legacy Audio Support SoundBlaster Pro compatibility in both Real Mode DOS and DOS windows is achieved through hardware SoundBlaster and OPL3 (FM) emulation registers. Legacy DMA over the PCI bus is supported on all major platforms utilizing PC/PCI, DDMA, or Philips' proprietary Legacy Accommodation ModeTM (LAMTM). DOS music synthesis includes stereo MIDI playback and quad/5.1 MIDI playback as well as FM emulation.
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Philips Semiconductors
Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator Architectural Overview
SAA7785
The SAA7785 ThunderBird AvengerTM is a multi-functional device that provides sound processing producing SoundBlaster-compatible emulation, DirectSound acceleration, 3D sound, spatialization, special effects, and 64-voice wavetable synthesis through the use of a Pine Digital Signal Processor (DSP) as the primary engine. Included within the ThunderBird Q3DIII are interfaces for an AC97 codec, I 2S I/O, MIDI port, standard analog joysticks, and an S/P DIF Consumer Output port. FIGURE 3 Block Diagram of a PC/AT System with the SAA7785 ThunderBird AvengerTM
Cache
PentiumTM CPU
HOST BUS
AGP Memory System Controller Graphics Multi I/O
ISA BUS
PCI to ISA Bridge
PCI BUS
ThunderBirdTM Audio Controller
AC97 CODEC 2/4 Channels (Primary)
AC97 CODEC Additional 2 channels
MIDI Port
Joystick
I2S
S/P DIF
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Philips Semiconductors
Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
SAA7785
The SAA7785 ThunderBird AvengerTM chip is designed to operate on any PCI system with the proper software support. Software support is required for non-DOS applications, such as Windows(tm) drivers. Non Pentium(tm) based system can also be supported with the additional software. Systems that provide DDMA or have the ISA bridge on the primary PCI bus are able to perform SoundBlaster emulation enabling the operation of legacy DOS based games. The SAA7785 ThunderBird AvengerTM chip provides two 8237 style DMA channels to perform legacy DMA cycles on selected systems. The same two 8237 channels provide Distributed DMA support as well. PC/PCI is also supported to provide legacy DMA support on chipsets that support said protocol. For systems that support neither DDMA nor PC/PCI, there is a software solution implemented as a TSR. DirectSound acceleration, both for 2D and 3D audio along with wavetable sample fetching, is accomplished using the SAA7785 ThunderBird Avenger TM chip PCI 2.1 bus master. This bus master provides the means for the SAA7785 ThunderBird AvengerTM chip to accelerate DirectSound audio streams as well as fetch wavetable sample for the 64 voice wavetable synthesis and effects algorithms. Wavetable sample fetching is always retrieved from system memory saving the cost of an external wavetable ROM. Downloadable sample sets, with software, are also supported using the bus master hardware. Additionally, the SAA7785 ThunderBird AvengerTM chip follows the AC97 Architecture to provide high quality audio by the use of one or more separate codecs. Serial DACs, as well as AC97 CODECs can be selected to providing audio into the analog world for low cost playback. Multi-channel AC97 CODECs can be used to provide up to 8 channels of audio output. A programmable DSP core is also provided to run the audio algorithms for wavetable synthesis, FM synthesis, special effects such as reverb and chorus, along with sample rate conversion and data management. The imbedded DSP core and its peripherals are managed solely by the DSP and requires no intervention from the host. The host can DSP can pass messages to and from each domain to provide a host software interface into the DSP domain.
PCI Interface, Configuration, and Interrupt Serializer
The SAA7785 ThunderBird AvengerTM chip PCI interface is composed of master and slave state machines, an address/data/byte enable datapath, a bus arbiter for the two on chip masters, control logic for the master and slave internal busses, an interrupt serializer, and the standard PCI configuration register header. The standard PCI configuration header is also supported. Since the SAA7785 ThunderBird AvengerTM is a multi-function device, there are three PCI configuration spaces allocated for each function. The three functions are the audio device, the joystick and the 16650 UART. The purpose of the multiple configuration headers is to ensure PCI compliance and enable the operating system to select the correct software driver for each individual device. The Serial CFG Port is used to shift in subvendor specific data for each of the PCI configuration headers. The Serial CFG port is an industry standard I2CTM format. The configuration headers are included in the PCI interface to reduce inter-block routing. All other PCI configuration space registers are included in the blocks that utilize these registers.
Clocks and the PLL Subsystem
Clocks for operation of the SAA7785 ThunderBird AvengerTM are derived from two sources; an external crystal and bit clock from the AC97 CODEC. The SAA7785 ThunderBird Avenger TM PLL Subsystem derives its reference from the external crystal. The SAA7785 ThunderBird AvengerTM substem consists of a fixed layout PLL cell and a digital interface to the 8 bit PS bus. The PLL is designed to drive the clocks for the DSP subsystem. The implementation calls for the PLL to be utilized with complete programmable register interface to enable the tuning of the frequencies as necessary.
Multimedia Timer
The SAA7785 ThunderBird AvengerTM chip supplies a 20-bit, .84 uS resolution timer for game synchronization. The 1999 Nov 12 12
Philips Semiconductors
Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
SAA7785
timer data can be accessed as an I/O device. This timer can be used by game developers to keep track of time elapsed to synchronize the video to the audio stream. The timer can be polled or interrupt driven and is selectable by the user application.
DMA
DMA is for the Sound Blaster registers, the DSP Mastering Device (DMD), and the S/P DIF output. To cover as many systems as possible, the DMA interface supports three modes for legacy support: Mobile PC/PCI DMA Arbitration (PC/PCI), Distributed DMA (DDMA) and Legacy Accommodation Mode (LAM). Legacy Accommodation Mode allows the SAA7785 ThunderBird AvengerTM, in an architecturally compatible system, to snoop and snarf selected DMA cycles on the PCI bus that were intended to the ISA Bridge. If a chip set supports Distributed DMA, the SAA7785 ThunderBird AvengerTM will use this method since it is more efficient than LAM. Additionally, PC/PCI can be utilized as well if neither DDMA nor LAM are supported on the selected chip set.
AC Link
The SAA7785 ThunderBird AvengerTM chip provides support for the AC97 (V2.1) specification by supplying an AC Link interface to communicate with industry standard AC97 CODECs. Up to two CODECs can be used for a total of 8 possible outputs (4 stereo channels).
Sound Blaster Registers
The other device that requires DMA is the SoundBlaster registers. DMA is used to transfer SoundBlaster digital audio files from the host to a codec for playback in addition to providing a mailbox for other commands. In order for the DSP to emulate the Sound Blaster sound effects, a legacy register set must be implemented to capture these commands. These sixteen, 16-bit registers are used primarily to emulate SoundBlaster Pro register set as well as the SoundBlaster Pro mixer registers. These registers are used as a mailbox to the DSP data bus to deliver data to the SoundBlaster Emulation code. The SAA7785 ThunderBird AvengerTM chip supports DMA to the Sound Blaster that legacy code requires. All data transmitted over the SoundBlaster Registers is processed by the DSP to emulate the Sound Blaster Pro hardware.
OPL3 Registers and the FM Accelerators
The OPL3 register interface is a subset of the complete SoundBlaster register set. The OPL3 registers are separate to point out that the FM legacy is supported at the register level. The OPL3 registers simply pass FM synthesis commands to the SoundBlaster Emulation code and receive status from the same code.
Virtual Registers
The Virtual Registers interfaces the PCI bus and two substantial wavetable synthesis accelerators: the Sample Fetch and Address Generation accelerators. The Virtual Registers is responsible for setting up the PCI interface for master cycles data fetches and retrieving those fetches into a sample buffer. The Virtual Registers get commands from the Address Generation accelerator and turns them into PCI master requests. Once the data has been retrieved, the Virtual Register then instructs the Sample Fetch accelerator to process a block of data. Once the processing is complete, the Sample Fetch Accelerator notifies the Virtual Registers that all is clear and that new data can be processed.
Address Generation Accelerator
The Address Generation accelerator is a preprocessing unit for the sample fetching mechanism inside the Virtual Registers. The Address Generator will get a set of parameters from the DSP code on a per voice basis for either DirectSound processing or wavetable synthesis. Once these voice parameters are set, the hardware is instructed to translate
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Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
SAA7785
the addresses and fetch the audio samples from system memory. The Address Generator is also capable of looping without intervention from the DSP code. The DSP kills voices by instructing the Address Generator to stop fetching data. Once the samples are fetched, they are stored in the Virtual Register's input sample buffer for processing by the Sample Fetch Accelerator.
Sample Fetch Accelerator
The Sample Fetch accelerator is used to process audio samples fetched by the Virtual Registers and deliver them to the DSP code for further processing. This processing can include pitch shifting or sample rate conversion. The degree of pitch shifting is under direction of DSP code indicating the Sample Fetch accelerator is programmable. The input samples are taken from the Virtual Register's input sample buffer and stored in DSP memory space.
MIDI Registers and UART
An MPU401 compatible UART is supplied to enable external MIDI devices to use the SAA7785 ThunderBird AvengerTM chip synthesizers as well as its external device's own synthesizer. The MIDI register interface is used to pass the MIDI command stream from the host to the DSP firmware for parsing into synthesizer commands. The MPU401 UART always operates in "dumb" mode. Both the PCI and DSP can access the MIDI UART directly. Data is presented from/to the MPU401 Registers in a mailbox fashion to the MPU401 UART.
General Purpose Input/Output
There are seven general purpose I/O pins that are controlled by the PCI bus (128 pin version). No GPIOs are available in the 100 pin package.
PINE DSP Core
The Pine DSP core is a programmable 16-bit integer DSP with separate code and data busses (Harvard architecture). Main features of the DSP core include 2K x 16 data RAM, 64K word code and data space, 16 x 16 bit two's complement parallel multiplier with 32-bit product, single cycle multiply/accumulate instructions, 36-bit ALU, two 36-bit accumulators, six-general purpose 16-bit pointer registers, option for up to eight user-defined 16-bit registers, zero overhead looping, repeat and block-repeat instructions with one nesting level, shifting capability, automatic saturation mode on overflow while reading content of accumulators, divide and normalize step support. As noted on Figure 2, the DSP subsystem is supported by two dedicated Pine internal busses called the DSP code bus and the DSP data bus. All DSP peripherals are connected to the DSP data bus while the code bus is used for just that, DSP code ROM and RAM. Both the DSP code and data busses are 16-bit for the address and data lines on each bus. DSP code also enables the DSP core to act as a PCI bus master making it a powerful and flexible audio processing unit. DSP Interrupt Controller The DSP Interrupt Controller is a programmable, priority encoded device that encodes two interrupt signals to the Pine core. The DSP Interrupt Controller resides on the DSP data bus and is programmed by DSP code. Both sets of interrupt vectors feature an enable and status bit for each interrupt based device. DSP Memory Controller The DSP memory controller provides controls and decodes for the regular DSP data and code RAMs as well as the code ROMs. The Memory Controller also includes a patch mechanism to allow ROM code to be updated or fixed using a trapping device.
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Philips Semiconductors
Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator SERIAL PORT INTERFACES
OVERVIEW
SAA7785
The SAA7785 chip will contain an S/PDIF Consumer Grade transmit port and an I2S transmit/receive pair. These serial ports are designed to exchange digital audio data but can be used for any type of data transfer assuming the bandwidth is adequate. Currently, these ports are connected to the DSP data bus. The Inter-IC Sound Bus, or I2S Port, is a simple interface used to transfer digital data from one source to another. The interface is based on a continuous serial clock that determines the data rate along with the word select line and the data lines. An I2S port can be a master or a slave device. A master device drives the serial clock and word select lines while a slave device receives the clocking signals. The SAA7785 I2S ports are independently programmable to be either a master or a slave and for 32.0, 44.1 and 48.0KHz stereo data transfer. Also included is a Sony/Philips Digital Interface Format, or S/PDIF, serial port. This interface is generally used to transmit raw audio data but is also used to transfer AC-3 encoded data as well using DMA. The S/PDIF format is a synchronous interface with the clock encoded on the data stream. The S/PDIF ports support 32.0, 44.1 and 48.0KHz stereo data transfer up to 24 bits. The S/PDIF interface is IEC958 Consumer Grade compliant.
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Philips Semiconductors
Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
FIGURE 4 I2S SERIAL PORTS BLOCK DIAGRAM
SAA7785
Right Data Left Data
Transmit Shift Register
XDATA
Transmit Control Logic
XSCLK XWS
CCLK
I2S Ports Clock Divider
Receive Control Logic
RWS RSCLK
Left Data Right Data
Receive Shift Register
RDATA
DSP DATA BUS
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Philips Semiconductors
Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
FIGURE 5 S/PDIF TRANSMIT PORT BLOCK DIAGRAM Audio Data Holding Registers DSP DATA BUS Audio Data Shift Registers
SAA7785
Validity Bit Generation
Aux Data Holding Registers
Aux Data Shift Registers
Ctl/Channel Stat Holding Registers
Ctl/Channel Stat Shift Registers
MUX
Bi-Phase Mark Encoder
Line Driver
SPDO
User Data Holding Register
User Data Shift Register
S/PDIF XMT Port Status Register
S/PDIF XMT Control Logic CCLK DCLK
Preamble Generation
S/PDIF XMT Clock Divider
Parity Generation
VIRTUAL WRITE MASTER
Audio streams may be directed back to host memory from the DSP domain. The VWM has a data buffer capable of storing enough audio data to burst into the host memory. The VWM is a simplified version of DMA and has more stringent requirements on which and how many pages need to be allocated. Using the VWM, the system programmer can redirect audio streams processed by the SAA7785 ThunderBird AvengerTM device and use them in any other audio device that resides in the system. The VWM is more efficient than the DMA and should be the device of choice when redirecting audio streams back to the host. The device supports audio sample rates from 8 to 48 KHz.
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Philips Semiconductors
Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator Game Port
SAA7785
The SAA7785 ThunderBird AvengerTM Game Port interface is designed to emulate the PC-AT based legacy joystick operation as well as support of a digital joystick mode. The legacy or analog, type of operation is designed to support all legacy software that uses the original joystick address and the method for resolving the joystick axes positions. The Digital Mode is designed to reduce the joystick overhead by resolving the joystick position directly and to support applications that use DirectInput. The legacy joystick used a one shot multi-vibrator on each of the four joystick potentiometers. These one shots were set up to deliver a pulse that was proportional to the resistor value of the joystick potentiometers. Software would them poll the one shots to see if they had been set to the original value. The time it took for each axes to return to the original value was resolved into a position by the legacy software. The SAA7785 ThunderBird AvengerTM emulates the 558 based one shot circuit to support legacy games that use the PC-AT joystick. The joystick button values were routed directly to the system bus where only a decode was required to read the value of the button. Software would poll the buttons as well. All button and joystick axes data is returned in a single byte wide register. Game Port Legacy I/O Register This register is the legacy mode register for the 558 based joystick. When in "analog" mode, this register is aliased to respond to addresses at base + (0-7) . Reads from this register will poll the status of the joystick buttons and are used to resolve the position. Writes to this register will discharge the external capacitors to emulate the 558 one shots. Software can then poll the joystick register bit to resolve each of the joystick axes positions by timing. The joystick button register bits have meaning in both the digital and analog modes. The axes bits are only valid for analog mode. TABLE 3 Game Port 558-Based Register - GAMEPORT (RO) D7 JOYB_2 1 Name JOYB_2 JOYB_1 JOYA_2 JOYA_1 JOYB_Y JOYB_X JOYA_Y JOYA_X R/W RO RO RO RO RO RO RO RO D6 JOYB_1 1 D5 JOYA_2 1 D4 JOYA_1 1 D3 JOYB_Y 0 Function Joystick B button 2 status. The joystick button status bits are cleared when the respective joystick button is pressed. Joystick B button 1 status. Joystick A button 2 status. Joystick A button 1 status. Joystick B y-coordinate. Can also be referred to as position 3. Joystick B x-coordinate. Can also be referred to as position 2. Joystick A y-coordinate. Can also be referred to as position 1. Joystick A x-coordinate. Can also be referred to as position 0. D2 JOYB_X 0 D1 JOYA_Y 0 D0 JOYA_X 0
I/O GMBASE Offset 1h POR Value Bit 7 6 5 4 3 2 1 0
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Philips Semiconductors
Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator SAA7785 SIGNAL DEFINITIONS
PCI LOCAL BUS INTERFACE SIGNALS AD[31:0] PCI Address/Data
SAA7785
AD[31:0] contains a physical byte address during the first clock of a PCI transaction, and data during subsequent clocks. When the SAA7785 is a PCI master, AD[31:0] are outputs during the address phase of a transaction. They are either inputs or outputs during the data phase, depending on the type of PCI cycle in process. When the SAA7785 is a PCI slave, AD[31:0] are inputs during the address phase. They are either inputs or outputs during the data phase, depending on the type of PCI cycle in process. C/BE#[3:0] PCI Bus Command and Byte Enables C/BE#[3:0] defines the bus command during the first clock of a PCI transaction, and the byte enables during subsequent clocks. C/BE#[3:0] are outputs when the SAA7785 is a PCI bus master and inputs when it is a PCI bus slave. DEVSEL# PCI Bus Device Select When the SAA7785 is a PCI bus master the SAA7785 uses DEVSEL# to determine whether a master abort should occur if DEVSEL# is not sampled active by clock 5 of the transaction, or to determine whether a cycle is to be aborted or retried when a target-initiated termination occurs. When the SAA7785 is a PCI bus slave, DEVSEL# is an output which the SAA7785 drives LOW during the second PCLK after FRAME# assertion to the end of a transaction if the SAA7785 is selected. FRAME# PCI Bus Cycle Frame When the SAA7785 is a PCI master, FRAME# is an output which indicates the beginning of a SAA7785-initiated bus transaction. While FRAME# is asserted data transfers continue. When FRAME# is deasserted the transaction is in the final data phase. When the SAA7785 is a PCI slave, FRAME# is an input that initiates an I/O, memory or configuration register access if the SAA7785 is selected for the transaction. The SAA7785 latches the C/BE#[3:0] and AD[31:0] signals on the PCLK edge on which it first samples FRAME# active. IRDY# PCI Bus Initiator Ready When the SAA7785 is a PCI master, IRDY# is an output which indicates the SAA7785's ability to complete the data phase of the current transaction. It is always asserted from the PCLK cycle after FRAME# is asserted to the last clock of the transaction. When the SAA7785 is a PCI slave, IRDY# is an input which causes the SAA7785 to hold-off completion of a read or write cycle until sampled active.
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Philips Semiconductors
Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
STOP# PCI Bus Stop (Target Initiated Termination)
SAA7785
When the SAA7785 is a PCI master, STOP# is an input which causes the SAA7785 to complete, abort or retry the transfer, depending on the state of TRDY# and DEVSEL#. When the SAA7785 is a PCI slave, it drives STOP# as active (LOW) to terminate or retry a transaction. TRDY# PCI Bus Target Ready When the SAA7785 is a PCI master, TRDY# is an input which indicates the target agent's ability to complete the data phase of the transaction. After initiation of a PCI bus transaction, the SAA7785 inserts wait cycles until TRDY# is sampled active. When the SAA7785 is a PCI slave, it drives TRDY# active to indicate that the SAA7785 has sampled the data from AD[31:0] during a write phase, or presented valid data on AD[31:0] during a read phase. PAR PCI Bus Parity When the SAA7785 is a PCI master, it drives PAR to reflect the correct value for even parity on the AD[31:0] and C/BE#[3:0] buses one clock after the address phase and after each write data phases. When the SAA7785 is a PCI slave, it drives PAR to reflect the correct value for even parity on the AD[31:0] and C/BE#[3:0] buses one clock after completion of each read data phase. PCREQ# PC/PCI DMA Request This signal requests DMA series from an external chipset that supports PC/PCI protocols. The SAA7785 chip asserts PCGNT# according to the desired DMA channel required by either the SoundBlaster or AC97 interfaces. The requested channel is encoded serially on the PCGNT# pin. The SAA7785 will become the bus owner when it receives an asserted PCGNT# signal. This handshaking is synchronous to PCLK. PCGNT# PC/PCI DMA Grant An asserted PCGNT# pin indicates that the external PC/PCI master arbiter has granted DMA services to the encoded DMA channel to the requesting DMA agent on the SAA7785 chip. REQ# PCI Bus Request This signal controls the PCI bus arbitration between the SAA7785 chip and the PCI master arbiter. When REQ# is asserted, the SAA7785 indicates a desire to become the PCI bus owner. The SAA7785 will become the bus owner when it receives an asserted grant signals (GNT# is LOW). This handshaking is synchronous to PCLK. REQ# is three-stated while RST# is active.
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Philips Semiconductors
Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
GNT# PCI Bus Grant
SAA7785
An asserted GNT# pin indicates that the PCI master arbiter has granted bus ownership to the SAA7785 chip. INTA# PCI Bus Interrupt A The interrupt output is a PCI compatible active low level sensitive interrupt. It is only used if the SAA7785 is used in a non Common Architecture system. Otherwise it is tri-stated. It is driven low when any of the internal interrupts are asserted. PERR# PCI Bus Parity Error This signal indicates a data parity error for any cycle type other than a Special Cycle command. PERR# is made active two clocks after the completion of the data phase which caused the parity error. This error signal may result in the generation of a non-maskable interrupt (NMI) or other high priority interrupt sent to the CPU. SERR# PCI Bus System Error This signal indicates an address parity error, data parity errors on Special Cycle commands or any other catastrophic system error. SERR# is an open-drain bidirectional pin which is driven low for a single PCLK cycle by the agent reporting the error. This error may result in the generation of a non-maskable interrupt (NMI) or other high priority interrupt sent to the CPU. IDSEL Initialization Device Select IDSEL is used as a chip select during configuration register read and write operations. One system board address line from AD[31:11] is used as IDSEL to select the SAA7785 configuration space in the SAA7785 chip when used on the PCI bus. CLKRUN# PCI Bus Clock Run Request The SAA7785 uses CLKRUN# according to the Mobile PCI protocol to start the PCI clock or keep the clock running whenever an internal PCI device requires it. PCLK PCI Bus Clock Input PCLK is the PCI bus clock input. It is used to synchronize all PCI bus operations and typically runs at 33MHz. RST# PCI Bus Reset An active low version of the system reset, this signal causes the PCI interface to return to the idle states in all state machines and asynchronously three-states all PCI bus signals. All registers will be reset to their default values as well. The CODEC interface line should be all driven inactive along with the external memory interface. This reset will assert the DSP reset. PME# PCI Bus Power Management Event Reserved.
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Philips Semiconductors
Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
PCI GENERAL PURPOSE I/O PGPIO[7:0] PCI General Purpose Input/Outputs
SAA7785
These eight pins are used as controls or data to devices external to the SAA7785 chip. Each are independently controlled.
TEST INTERFACE/SERIAL CONFIGURATION PORT NAND#/CFGDAT NAND Tree Test Enable/Serial Configuration Data When this pin is pulled low and RST# is pulsed asserted, all output and I/O pins of the SAA7785 will be forced into a three-state condition. Pulsed assertion of the RST# signal will release the SAA7785 from this test mode. If this pin is pulled high during PCI reset, then it is used to shift in PCI configuration data for the Subsystem ID and the Subsystem Vendor ID in each of the PCI configuration headers present in the SAA7785 chip. The Serial Configuration Port is a standard I2C interface. This line should never be pulled low. TRI#/CFGCLK Tri-State Test Enable/Serial Configuration Clock When this pin is pulled low and RST# is pulsed asserted, the SAA7785 will enter the parametric NAND tree test mode. The details of the NAND tree test mode are described later in this document. If this pin is pulled high during PCI reset, then this pin will supply the serial 400 KHz clock, derived from OSC, to an external serial EEPROM. CFGCLK is used to synchronize the serial configuration data.
GAME PORT INTERFACE JACX Joystick A X Axis This pin functions as an input for the joystick A X-position axis. JACY Joystick A Y Axis This pin functions as an input for the joystick A Y-position axis. JBCX Joystick B X Axis This pin functions as an input for the joystick B X-position axis. JBCY Joystick B Y Axis This pin functions as an input for the joystick B Y-position axis. JAB2 Joystick A Button 2 Interface This pin functions as an input for the joystick A button 2.
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Philips Semiconductors
Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
JAB1 Joystick A Button 1 Interface This pin functions as an input for the joystick A button 1. JBB2 Joystick B Button 2 Interface This pin functions as an input for the joystick B button 2. JBB1 Joystick B Button 1 Interface This pin functions as an input for the joystick B button 1.
SAA7785
MIDI INTERFACE MIDIIN MIDI Serial Data Input This signal is part of the standard 2 wire MIDI interface. This input receives MIDI data at a rate of 31.25Kbaud. Optical isolation is required. MIDIOUT MIDI Serial Data Output This signal is part of the standard 2 wire MIDI interface. This output transmits MIDI data at a rate of 31.25Kbaud. Optical isolation is required.
AC'97 CODEC INTERFACE SYNC AC'97 Codec Synchronization/Frame Output This signal is used to frame the tag packet from the AC link designer from the SAA7785 chip. BIT_CLK AC'97 Data Bit Clock This signal is used to clock synchronous data on the AC link interface. SDATA_OUT AC'97 Serial Data Out This is the time division multiplexed serial output data stream from the SAA7785 controller. SDATA_IN0 AC'97 Serial Data In Port 0 This is the time division multiplexed serial input data stream from the primary external AC'97 codec. SDATA_IN1 AC'97 Serial Data In Port 1 This is the time division multiplexed serial input data stream from the secondary external AC'97 codec.
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Philips Semiconductors
Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
AC_RST_N# AC'97 Master Reset
SAA7785
The external AC'97 codec has a master reset line which is has a separate control. The codec status must report a ready before any audio or modem data is transmitted to the codec.
DSP SERIAL PORTS/GENERAL PURPOSE I/O SPDO Sony/Philips Digital Interface Format Output Port Consumer format S/PDIF Output Port. The output characteristic of this pad approximates the RS422 interface. SPDI Sony/Philips Digital Interface Format Input Port Reserved. RWS Inter-IC Sound Bus Receive Port Word Select Clock/DSP General Purpose I/O 0 When the I2S is configured as a master, this pin will output a word clock at the frequency selected by the user. When configured as a slave, the receive port will synchronize the left or right channel data to this signal. RSCK Inter-IC Sound Bus Receive Port Bit Clock/DSP General Purpose I/O 1 When the I2S is configured as a master, this pin will output a bit clock. When configured as a slave, the receive port will shift in data from the RSD data stream using RSCK as an input. RSD Inter-IC Sound Bus Receive Port Data/DSP General Purpose I/O 2 This pin is the input data stream for the I2S receive port. TWS Inter-IC Sound Bus Transmit Port Word Select Clock When the I2S is configured as a master, this pin will output a word clock at the frequency selected by the user. When configured as a slave, the receive port will synchronize the left or right channel data to this signal. TSCK Inter-IC Sound Bus Transmit Port Bit Clock When the I2S is configured as a master, this pin will output a bit clock. When configured as a slave, the transmit port will shift out data from the TSD data stream using TSCK as an input. TSD Inter-IC Sound Bus Transmit Port Data This pin is the output data stream for the I2S transmit port.
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Philips Semiconductors
Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
PLL/DSPCLK SUBSYSTEM INTERFACE CCLK CODEC Clock Input
SAA7785
This pin is the raw 24.576MHz clock from the AC'97 crystal. The CCLK clock is used to provide a fixed time base for many functions within the SAA7785 device. DSPCLK DSP Clock Input This pin can be used as the clock input for the SAA7785 for the DSP subsystem in place of the PLL driving the clock. DSPCLK is also used to drive the DSP subsystem for controllability during testing. PSUB PLL Substrate This pin supplies the bias for the guard ring on the PLL core. Connect this to a clean analog supply ground. PLLAPWR PLL Analog Power Analog power supply for the PLL. Be sure the analog supply is isolated from the 3 volt digital supply. PLLAGND PLL Analog Ground Analog ground for the PLL. This power supply is sensitive to noise and should be handled carefully.
POWER AND GROUND PINS VDDIC VSSIC VSS VDD NWELL Core Power 3 volt power supply for the core of the chip. Core Ground Ground reference for the core of the chip. Ring Ground Ground reference for the pad interfaces of the chip. Ring Power 3 volt supply for the pad interfaces of the chip. External N-Well Bias Tie these pins to 5v for proper 5 volt tolerant operation. The 5v supply must be powered up before the 3v supply. Likewise, the 3v supply must be powered down before the 5v supply. PLEASE READ THE CAUTIONS IN Section 4.1, POWER SUPPLY OPERATING REQUIREMENTS ***** MUST READ *****
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Philips Semiconductors
Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
DSP EXTERNAL MEMORY INTERFACE MA[14:0] External Memory Address
SAA7785
Address lines for the external SRAM devices. The external memory interface can be used for DSP code space if the EXT_SRAM_EN (in HDCFG, bit 5) is set. Otherwise, the DSP will use internal ROM as the code source. MD[15:0] External Memory Data Bus Word wide data bus for the external SRAM. Use 6ns memory for maximum DSP performance. MCS# External Memory Chip Select Chip select line for the external SRAM devices. MWE# External Memory Read/Write Control Selects the external SRAM for reading or writing.
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Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator SAA7785 ThunderBird AvengerTM Functional Block Descriptions Register Table Document Description and Example
The next table gives an example of how registers are documented in this specification. TABLE 4 SPACE Offset nnh POR Value Example Register - REGEX (RW/RO) D15 R 0 D7 D14 R 0 D6 D13 R 0 D5 D12 R 0 D4 D11 R 0 D3 D10 R 0 D2 D9 R 0 D1
SAA7785
D8 R 0 D0
EXDATA[7:0] POR Value Bit 15:8 7:0 R EXDATA Name 0 R/W RO RW 0 0 0 0 Function Reserved. These bits always return zeros. Example data. The example data for all to see. 0 0 0
In the above table example, the EXAMPLE REGISTER text would be a descriptive title for the register that we wish to detail. Following the register description would be a register mnemonic used in register summary tables and the like. In this example the mnemonic is REGEX. Following the mnemonic is the read/write access allowed into this register. If the entire register is readable and writable, then the RW key is assigned. If some bits are read/write while others are read only, then the key will indicate this fact. In the example, this register has both read/write and read only bits. The register memory map location is marked in the table cell marked SPACE. SPACE could be substituted with PCI CFG n (for PCI configuration register space for function n), IOBASE (for an I/O space register with an IOBASE specified in a configuration register), DSP DATA (for DSP data memory mapped registers), MEM MSTR (indicating a PCI master in memory space), and DSP CODE (indicating a DSP code memory mapped register. Just below the SPACE marker is the offset from the base address specified in the SPACE field. The rest of the table should be obvious. SAA7785 ThunderBird AvengerTM PCI Interface Overview The SSA7785 ThunderBird AvengerTM chip PCI interface is designed to interface the external PCI bus interface to all of the selected devices in the SSA7785 ThunderBird AvengerTM chip. The PCI interface composed of master and slave state machines, an address/data/byte enable datapath, a bus arbiter for the two on chip masters, control logic for the master and slave internal busses, and standard PCI configuration register headers. The Interrupt Serializer will be discussed in a later chapter. This section of the specification will describe the PCI interface in more detail along with design considerations for both the slave, master, and datapath. The configuration header will be discussed in the SSA7785 ThunderBird AvengerTM PCI Configuration Registers section of this specification. The discussion will begin with the PCI master and target systems. The PCI bus master has the capability to burst double words to/from the two internal bus masters, the Distributed DMA and the Virtual Registers. The full address range is supported for these master devices. Since there are two masters, an arbiter is required to determine priority between the two devices. Details on the arbiter can be found in the PCI master section.
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Philips Semiconductors
Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
SAA7785
The PCI datapath block contains the multiplexors and registers to steer the data to and from the PCI interfaces. The data is de-multiplexed from the external PCI interface to the internal master and slave busses. Control logic from the master and slave devices control the datapath. The SSA7785 ThunderBird AvengerTM is considered a multi-function device since the operating system may wish to load different drivers for certain functions. These functions are the audio subsystem, the joystick and the 16650 UART. Each of these major functions must have a separate PCI configuration space. The standard PCI configuration header for these three functions are supported in the PCI interface. The SSA7785 ThunderBird AvengerTM PCI interface responds to and initiates PCI cycles with positive decoding according to the PCI 2.1 specification. The interface asserts DEVSEL# after the first clock following FRAME# making it a medium responder. For specific LAM cycles, the SSA7785 ThunderBird AvengerTM will be a fast responder. SSA7785 ThunderBird AvengerTM indicates which cycles the PCI interface responds to or initiates. TABLE 5 c/be#[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 PCI Bus Command Definitions and SSA7785 ThunderBird AvengerTM Responses Command Type Interrupt Acknowledge Special Cycle I/O Read I/O Write Reserved Reserved Memory Read Memory Write Reserved Reserved Configuration Read SSA7785 ThunderBird AvengerTM Response to Cycle This cycle is not claimed. This cycle is not claimed. All I/O Read cycles directed to the SSA7785 ThunderBird AvengerTM are claimed by the target interface. All I/O Write cycles directed to the SSA7785 ThunderBird AvengerTM are claimed by the target interface. This cycle is not claimed. This cycle is not claimed. This cycle is not claimed. This cycle is not claimed. This cycle is not claimed. This cycle is not claimed. All Configuration Read cycles are claimed by the target interface provided IDSEL is sampled asserted during the address/cmd phase. All Configuration Write cycles are claimed by the target interface provided IDSEL is sampled asserted during the address/cmd phase. This cycle is not claimed. The SSA7785 ThunderBird AvengerTM supports 32-bit addresses only. This cycle is not claimed. This cycle is not claimed.
1011
Configuration Write
1100 1101 1110 1111
Memory Read Multiple Dual Address Cycle Memory Read Line Memory Write and Invalidate
The SSA7785 ThunderBird AvengerTM will respond to byte, word, tri-byte or double word access for configuration read and configuration write cycles provided PCI addressing rules are followed. Byte and word width accesses allowed for I/O cycles depend largely on the target I/O device. In general, 24-bit and 32-bit accesses are not allowed to I/O devices and will result in a target abort. The SSA7785 ThunderBird AvengerTM performs double word accesses when initiating
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Philips Semiconductors
Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
SAA7785
master cycles. Note that the SSA7785 ThunderBird AvengerTM cannot initiate a master cycle to itself. SSA7785 ThunderBird AvengerTM summarizes the access rules for configuration and I/O cycles. TABLE 6 BIT Width Device Access Rules Data Width Any
Device PCI Configuration Registers
Cycle Types Config Read Config Write
Comments Follow PCI addressing rules, otherwise assert a target abort. Note that configuration registers, no matter where they are, are accessed by configuration cycles only. Note that the PLL will only allow 8 bit configuration accesses, the Virtual Registers TBLBASE registers are 32 bit access only, and the VRCFG is 16 bit access only. Any other access will result in a target abort. For PIO type accesses, only 16 bit I/O cycles are allowed, other wise a target abort will result.
Game Port AC'97 Codec DMA Interface Sound Blaster Registers Virtual Registers Host/DSP Interface
I/O Read I/O Write I/O Read I/O Write I/O R/W I/O Read I/O Write Mem Read I/O Read I/O Write
8 16 Any 8 Any 8,16
Any other access will result in a target abort. Follow PCI addressing rules. Usually, only 16 bit accesses will be used to download and access the DSP. Byte wide are also allowed for DSP configuration accesses. Word accesses must be on word boundaries. Any other access will result in a target abort. Any other access will result in a target abort.
MPU401 Registers 16650 UART
I/O Read I/O Write I/O Read I/O Write
8 8
The PCI interface consists of three major blocks, the PCI master interface, the PCI slave interface and the PCI datapath. The PCI master interface contains the master state machine, the master control logic, and the PM bus arbiter. The PCI slave interface contains the target state machine, the target control logic and configuration register headers. The PCI datapath is the de-multiplexing logic for the address, data and byte enable data paths for the PS and PM busses. The PM and PS busses are described in detail in the SSA7785 ThunderBird AvengerTM Internal Busses section. Partitioning of these PCI blocks are done in this manner to reduce block inter-connectivity and to provide an interface between the three major sections of the PCI interface. PCI Master Interface The SSA7785 ThunderBird AvengerTM PCI master interface performs the memory read and write cycles initiated by the DMA or Virtual Registers blocks. The major components of the PCI master interface are the master state machine, the PM bus arbiter and the master control logic. Each of the functional blocks will be discussed in detail.
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Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
PCI Master State Machine
SAA7785
This block will performs the handshaking between the PCI interface and the PM internal bus. The PCI master will perform bursting in a linear incrementing type fashion. The PCI master state machine may also wish to provide a target lockout signal. This signal prevents the PCI target interface from responding to any master signals. PC/PCI Legacy Support The PCI block supports the PC/PCI sideband signals for legacy support of the soundblaster. The PC/PCI can be enabled by a configuration register bit and one channel selected. The PCI slave block will provide the serial encoded request signal (PCREQ#) in response to a request from the soundblaster and decode the serial encoded PCGNT# line. The PCI slave will then claim I/O writes to address 0000h or 0004h with the PCGNT# line asserted as writes to the SoundBlaster and pass the data to the SoundBlaster. PCI Target State Machine The PCI target state machine controls all SSA7785 ThunderBird AvengerTM target responses on the PCI bus in addition to handling the PS internal bus. PCI Target Control Logic The target control logic handles the address decoding for the ps_NNNcs# signals, bus command decoding for the ps_XXXrd# and ps_XXXwr# signals, determination of target abort conditions, and data path/pad control logic from the target interface. Also included in this logic are the controls for the PCI datapath and I/O pads. These controls are sent to the datapath logic where they are combined with the master controls and then sent to the datapath and pad devices. The control logic also includes an interface to the PCI configuration headers. Serial Configuration Port The Subsystem Vendor ID and Subsystem ID for each of the configuration headers presents a special case. These three 32 bit registers must be programmed by the Subsystem Vendor. It is impractical to hard wire the Subsystem ID registers since each Subsystem Vendor will have a unique ID. Therefore an external serial EEROM device is used to download the proper values into the ID registers after reset and before begin read by the BIOS or other configuration software. The PCI interface should force a retry if any of the subsystem registers have not completed a loading. The Serial Configuration Port is a standard two pin I 2C interface. The ThunderBird Q3DIII will supply the 400 KHz clock to the external serial EEPROM on the CFGCLK pin. The serial data stream will arrive on the CFGDAT input pin. Please refer to a 24LC00 128 bit I2C Bus Serial EEPROM data sheet for interface protocols and timings. Serial Configuration Port Programming The SSA7785 ThunderBird AvengerTM uses an inexpensive external EEPROM, programmed before installation, to download the Subsystem Vendor ID and Subsystem ID registers for each function for a total of 96 bits (six 16 bit registers). The recommended device, a Microchip 24LC01B 1K Bit (128 Byte) Serial EEPROM, can be programmed using a conventional DATA I/O programmer.
+5V CFGDAT ThunderBird CFGCLK SDA WP
EEPROM SCL
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Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
FIGURE 6
SAA7785
In each of the three SSA7785 ThunderBird AvengerTM functions PCI configuration space there is a Subsystem Vendor ID register at an offset of 2Ch and a Subsystem ID register at an offset of 2Eh. Each register is 16 bits in length and is write-only by the serial EEPROM and read-only from the PCI interface. The data from the EEPROM is loaded into the registers immediately after PCI reset. If no EEPROM is detected, the default values are loaded and shown in SSA7785 ThunderBird AvengerTM and reflect the default values for the System ID and Vendor ID for that function. TABLE 7 Subsystem Register Default Values Function 0 0 1 1 2 2 Device Type Audio Subsystem Audio Subsystem Joystick Joystick 16650 UART 16650 UART Offset 2Ch 2Eh 2Ch 2Eh 2Ch 2Eh Register Name Subsystem Vendor ID Subsystem ID Subsystem Vendor ID Subsystem ID Subsystem Vendor ID Subsystem ID Default Value 1004h 0304h 1004h 0305h 1004h 0306h
The EEPROM contains bits 000h through 3FFh. Only bits 000h through 05Fh are utilized to program the Subsystem ID and Subsystem Vendor ID registers. The bit assignments between the EEPROM and the configuration registers are shown in SSA7785 ThunderBird AvengerTM. TABLE 8 EEPROM BIT Assignments to Subsystem Registers
Function 1 - Joystick Subsystem Vendor ID - Offset 2Ch EEPROM Bit # 020h 021h 022h 023h 024h 025h 026h 027h 028h 029h 02Ah 02Bh 02Ch 02Dh 02Eh Reg Bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Subsystem ID Offset 2Eh EEPROM Bit # 030h 031h 032h 033h 034h 035h 036h 037h 038h 039h 03Ah 03Bh 03Ch 03Dh 03Eh Reg Bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Function 2 - 16650 Modem UART Subsystem Vendor ID - Offset 2Ch EEPROM Bit # 040h 041h 042h 043h 044h 045h 046h 047h 048h 049h 04Ah 04Bh 04Ch 04Dh 04Eh Reg Bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Subsystem ID Offset 2Eh EEPROM Bit # 050h 051h 052h 053h 054h 055h 056h 057h 058h 059h 05Ah 05Bh 05Ch 05Dh 05Eh Reg Bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Function 0 - Audio Subsystem Subsystem Vendor ID - Offset 2Ch EEPROM Bit # 000h 001h 002h 003h 004h 005h 006h 007h 008h 009h 00Ah 00Bh 00Ch 00Dh 00Eh Reg Bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Subsystem ID Offset 2Eh EEPROM Bit # 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh Reg Bit # 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
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Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
SAA7785
Function 0 - Audio Subsystem Subsystem Vendor ID - Offset 2Ch EEPROM Bit # 00Fh Reg Bit # 0 Subsystem ID Offset 2Eh EEPROM Bit # 01Fh Reg Bit # 0
Function 1 - Joystick Subsystem Vendor ID - Offset 2Ch EEPROM Bit # 02Fh Reg Bit # 0 Subsystem ID Offset 2Eh EEPROM Bit # 03Fh Reg Bit # 0
Function 2 - 16650 Modem UART Subsystem Vendor ID - Offset 2Ch EEPROM Bit # 04Fh Reg Bit # 0 Subsystem ID Offset 2Eh EEPROM Bit # 05Fh Reg Bit # 0
These bits correspond to Function 0, Subsystem ID (offset 2Eh) bits 2, 1, and 0, respectively. The Vendor should choose and ID that corresponds to the peripherals present and program the EEPROM accordingly. PCI Datapath The PCI datapath provides the flip flops to convert the external PCI interface address, data, command and byte enables busses to the internal PM and PS busses. PCI Configuration Register Since the SSA7785 ThunderBird AvengerTM is a multi-function device, there are three configuration headers. They are defined as the audio configuration header as function 0, the joystick configuration header as function 1, and the UART configuration header defined as function 2. Each configuration space is divided up into two groups, the registers that stay with the PCI interface and the registers that do not. This section will describe the PCI configuration registers that bunk with the PCI interface. These registers include the PCI standard configuration header registers and the base address registers for various blocks in the SSA7785 ThunderBird AvengerTM chip. To be more specific, the registers in the offset config space from 00h - 3Fh are the predefined PCI configuration header. All three PCI configuration header registers will reside with the PCI interface. The remainder of the registers are function specific and can be found in the block section itself. The following sections will detail each of the configuration header spaces for each of the SSA7785 ThunderBird AvengerTM functions: audio, joystick and UART. PCI Configuration Space 0 The following table is a summary of all the PCI configuration space registers. The registers that are block-mates with the PCI interface (offset 00h - 44h) will be detailed following SSA7785 ThunderBird AvengerTM. The remainder of the registers will be detailed with the blocks they control. TABLE 9 Byte 3 PCI Configuration Space 0 Register Map Byte 2
Device ID Status Class Code BIST Header Type Master Latency Timer SONGBASE SBBASE MDBASE ALBASE Reserved
Byte 1
Byte 0
Vendor ID Command Revision ID Cache Line Size
Offset
00h 04h 08h 0Ch 10h 14h 18h 1Ch 20-2Bh
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Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
SUBSYSTEM ID Reserved Max_Lat DMABBASE Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved TBLBASE0 TBLBASE1 TBLBASE2 TBLBASE3 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved DMAACCNT DMABCCNT DMAMASK Reserved DMACMD Reserved DMAAMODE DMABMODE Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved DMAACADR DMABCADR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved IRQCTL0 IRQCTL1 IRQCTL2 IRQCTL3 IRQCTL4 IRQCTL5 IRQCTL6 IRQCTL7 COMARCH0 Reserved TESTCTL0 Reserved Reserved Reserved DPLLCTL0 DPLLCTL1 DPLLCTL2 DMACFG Reserved HDCFG Reserved Reserved VRCFG TIMRCFG0 MSCCFG ACLCFG0 Min_Gnt Interrupt Pin DMAABASE Interrupt Line SUBSYSTEM VENDOR ID
SAA7785
2Ch 30-3Bh 3Ch 40h 44-57h 58h 5Ch 60h 64h 68h 6Ch 70h 74-77h 78h 7Ch 80h 84-87h 88h 8C-8Fhh 90h 94h 98h 9Ch A0h A4h A8h ACh B0h B4h B8h BCh C0h C4-EFh F0h F4h F8h FCh
TABLE 10 PCI CFG 0 Offset 00h POR Value
Vendor ID Register - VENDOR_ID (RO) D15 D14 D13 D12 D11 D10 D9 D8
VENDOR_ID[15:8] 0 0 0 1 0 0 0 0
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Philips Semiconductors
Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
SAA7785
D7
D6
D5
D4
D3
D2
D1
D0
VENDOR_ID[7:0] POR Value 0 0 0 0 0 1 0 0
Bit 15:0
Name VENDOR_ID
R/W RO
Function The PCI Vendor ID for Philips Semiconductors (VLSI) is 1004h.
TABLE 11 PCI CFG 0 Offset 02h POR Value
Device ID Register - DEVICE_ID (RO) D15 D14 D13 D12 D11 D10 D9 D8
DEVICE_ID[15:8] 0 0 0 0 0 0 1 1
D7
D6
D5
D4
D3
D2
D1
D0
DEVICE_ID[7:0] POR Value 0 0 0 0 0 1 0 0
Bit 15:0
Name DEVICE_ID
R/W RO
Function The Device ID for the SSA7785 ThunderBird AvengerTM, function 0 is 0304h.
TABLE 12 PCI CFG 0 Offset 04h POR Value
Command Register - COMMAND (RO/RW) D15 R 0 D14 R 0 D13 R 0 D12 R 0 D11 R 0 D10 R 0 D9 FBACK_ ENB 0 D8 SERR_R ESP 0
D7 STEPPING POR Value 0
D6 PERR_ RESP 0
D5 SNOOP_ ENB 0
D4 MEM_ INV_EN 0
D3 SPEC_ CNTL 0
D2 MAST_ CNTL 0
D1 MEM_ CNTL 0
D0 IO_ CNTL 0
Bit 15:10 R
Name
R/W RO
Function Reserved. These bits always return zero.
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Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
SAA7785
Bit 9
Name FBACK_ENB
R/W RO
Function Fast Back-to-Back Enable: the SSA7785 ThunderBird AvengerTM, function 0 does not support fast back to back master cycles therefore this bit always returns a zero. System Error Response: When set to 1, the SSA7785 ThunderBird AvengerTM, function 0 responds to detected PCI bus address parity errors by asserting SERR#. When 0, the SSA7785 ThunderBird AvengerTM ignores these errors. Address / Data Stepping: Always returns 0. Parity Error Response: When set to 1, the SSA7785 ThunderBird AvengerTM, function 0 responds to detected PCI bus data parity errors by asserting PERR#. When 0, the SSA7785 ThunderBird AvengerTM ignores PCI bus data parity errors. VGA Snoop Enable. The SSA7785 ThunderBird AvengerTM, function 0 does not support VGA snoop enable, therefore this bit always returns a zero. Memory Write and Invalidate Enable: Always returns 0. Special Cycle Control: Controls the devices ability to respond to Special Cycle Operations. A value of 0 causes the SSA7785 ThunderBird AvengerTM, function 0 to ignore all Special Cycles. Master Control: Controls the devices ability to act as a master on the PCI bus. A value of 0 disables the ability of the SSA7785 ThunderBird AvengerTM, function 0, to act as a primary PCI master. A value of 1 enables the ThunderBird Q3DIII, function 0 to become a PCI bus master. Memory Response Control: The SSA7785 ThunderBird AvengerTM, function 0 does not support target memory cycles therefore this bit always returns a zero. I/O Response Control: Controls the SSA7785 ThunderBird AvengerTM, function 0's response to I/O space. A value of 0 disables the device response. A value of 1 allows the device to respond to I/O space accesses.
8
SERR_RESP
RW
7 6
STEPPING PERR_RESP
RO RW
5 4 3
SNOOP_ENB MEM_INV_EN SPEC_CNTL
RO RO RO
2
MAST_CNTL
RW
1
MEM_CNTL
RO
0
IO_CNTL
RW
TABLE 13 PCI CFG 0 Offset 06h POR Value
Status Register - Status (RO/RW) D15 R_PERR 0 D14 S_SERR 0 D13 SM_ ABORT 0 D12 RT_ ABORT 0 D11 ST_ ABORT 0 0 1 0 D10 D9 D8 S_PERR
DEVSEL_TMG
D7 F_ BK2BK POR Value 1
D6 UDF 0
D5 MHz66 0
D4 R 0
D3 R 0
D2 R 0
D1 R 0
D0 R 0
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Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
SAA7785
Bit 15
Name R_PERR
R/W RC
Function Received Parity Error: When set to 1, this bit indicates that the SSA7785 ThunderBird AvengerTM, function 0 has detected a PCI bus parity error at least once since this bit was last reset. Signalled System Error: When set to 1, this bit indicates that the SSA7785 ThunderBird AvengerTM, function 0 has reported a system error on the SERR# signal at least once since this bit was last reset. Signalled Master Abort: When set to 1, this bit indicates that the SSA7785 ThunderBird AvengerTM, function 0 (acting as a master) had to initiate a master abort at least once since this bit was last reset. Received Target Abort: When set to 1, this bit indicates that the SSA7785 ThunderBird AvengerTM, function 0 (acting as a master) has received a target abort at least once since this bit was last reset. Signalled Target Abort: When set to 1, this bit indicates that the SSA7785 ThunderBird AvengerTM, function 0 has signalled a target abort at least once since this bit was last reset. DEVSEL Timing: This field indicates the timing of the DEVSEL output (when a PCI master is accessing a SSA7785 ThunderBird AvengerTM, function 0 resource). It always returns 01 (Bin). 00 = Fast 01 = Medium (Default Timing) 10 = Slow
14
S_SERR
RC
13
SM_ABORT
RC
12
RT_ABORT
RC
11
ST_ABORT
RC
10:9
DEVSEL_TM G
RO
8
S_PERR
RC
Signalled Parity Error: When set to 1, this bit indicates that the SSA7785 ThunderBird AvengerTM, function 0 was a bus master for a cycle in which PERR# was activated. This bit cannot be set if the PERR_RESP bit in the command register is not enabled. Always returns 1 to indicate support of fast back to back cycles when the SSA7785 ThunderBird AvengerTM, function 0 is the target. User Definable Features. Always returns 0. 66 MHzMHz Capable. Always returns 0. Reserved. These bits always return zero.
7 6 5 4:0
F_BK2BK UDF MHz66 R
RO RO RO RO
Note: An RC indicates that this bit can be reset to 0 by writing a 1. Writing a zero leaves this bit unchanged. TABLE 14 PCI CFG 0 Offset 08h POR Value 0 0 0 Revision ID Register - REVISION (RO) D7 D6 D5 D4 D3 D2 D1 D0
REVISION_ID[7:0] 1 1 0 0 1
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Philips Semiconductors
Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
SAA7785
Bit 7:0
Name REVISION_ID
R/W RO
Function The current revision ID for the SSA7785 ThunderBird AvengerTM, function 0, the audio subsystem.
TABLE 15 PCI CFG 0 Offset 09h POR Value
Class Code Register - CLASS (RO) D23 D22 D21 D20 D19 D18 D17 D16
BASE_CLASS[7:0] 0 0 0 0 0 1 0 0
D15
D14
D13
D12
D11
D10
D9
D8
SUB_CLASS[7:0] POR Value 0 0 0 0 0 0 0 1
D7
D6
D5
D4
D3
D2
D1
D0
PGM_IFACE[7:0] POR Value 0 0 0 0 0 0 0 0
Bit 23:16 15:8 7:0
Name BASE_CLASS SUB_CLASS PGM_IFACE
R/W RO RO RO
Function The base class of 04h describes a PCI multimedia device. The sub class of 01h describes a PCI audio multimedia device. Device generic function identification.
TABLE 16 PCI CFG 0 Offset 0Ch POR Value
CACHELINE Size Register - CACHELINE (RO) D7 D6 D5 D4 D3 D2 D1 D0
CACHELINE[7:0] 0 0 0 0 0 0 0 0
Bit 7:0
Name CACHELINE
R/W RO
Function Reserved for cache line size indicator.
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Philips Semiconductors
Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
TABLE 17 PCI CFG 0 Offset 0Dh POR Value 0 0 0 Master Latency Timer Register - LATIME (RW) D7 D6 D5 D4 D3 D2 D1
SAA7785
D0
LATIME[7:0] 0 0 0 0 0
Bit 7:0
Name LATIME
R/W RW
Function The primary bus latency timer specifies the number of primary clocks that the primary master may consume. The timer is reloaded at each assertion of FRAME# by the primary master. If the primary master loses its bus grant, then it must relinquish the bus after the timer expires.
TABLE 18 PCI CFG 0 Offset 0Eh POR Value
Header Type Register - HEADER (RO) D7 MULTI_ FN 1 0 0 0 0 0 0 0 D6 D5 D4 D3 HEADER[6:0] D2 D1 D0
Bit 7
Name MULTI_FN
R/W RO
Function A 1 indicates that the SSA7785 ThunderBird AvengerTM is a multi-function device. The three PCI configuration headers are accessed by the configuration cycle address bits 10-8. The function definitions are as follows: 0 = Audio Subsystem 1 = Joystick 2 = 16650 UART
6:0
HEADER
RO
Header Type. A 00h indicates this device is a not a PCI-to-PCI bridge.
TABLE 19 PCI CFG 0 Offset 0Fh POR Value
BIST Register - BIST (RO) D7 BIST 0 D6 START 0 D5 R 0 D4 R 0 0 0 D3 D2 D1 D0
CODE[3:0] 0 0
Bit 7
Name BIST
R/W RO
Function BIST capable. BIST is not supported in the SSA7785 ThunderBird AvengerTM, function 0 at this revision. It may be desired to include a BIST test for the DSP at a later time.
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Philips Semiconductors
Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
SAA7785
Bit 6
Name START
R/W RO
Function If BIST capable, this bit will start the BIST. Writing a 1 will start the test and the BIST should write this bit to a zero when complete. Software should fail the device if the BIST is not complete after 2 seconds. Reserved. These bits always return zero. Completion Code. A value of zero means the device has passed its test. Non-zero values means the device has failed using device specific failure codes.
5:4 3:0
R CODE
RO RO
SSA7785 ThunderBird AvengerTM CFG Space 0 Non-Legacy Base Address Registers The Thunderbird Base Address Register (SONGBASE) is used to I/O map all of the non-legacy I/O devices in the SSA7785 ThunderBird AvengerTM chip. The SONGBASE register maps the two DMA channels, the AC Link registers, the Host/DSP interface, the Serial Port interfaces, and the Multimedia Timer. The offset index for each of the devices are shown below: SSA7785 ThunderBird AvengerTM Non-Legacy I/O Device Map Device Name Byte 3 TMCOUNT2 Multimedia Timer Reserved Reserved Reserved Reserved Serial Ports Reserved Reserved Reserved HDPCTL Host/DSP Interface HDDLA Reserved Reserved ACDATA AC Link Interface ACSTAT ACPCML ACPCMR Serial IRQ Thunderbird Reserved Reserved Reserved Reserved Reserved IRQCTL Byte 2 TMCOUNT1 Reserved Reserved Reserved Byte 1 TMCOUNT0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved HDDATA HDPSTT HDDLD Reserved ACADDR ACCTRL Byte 0 TMSTAT Reserved Reserved Reserved Offset
00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch 40h 44-7Fh
TABLE 20 PCI CFG 0 Offset 10h POR Value
ThunderBird Base Address Register - Songbase (RW/RO) D31 D30 D29 D28 D27 D26 D25 D24
SONGBASE[31:24] 0 0 0 0 0 0 0 0
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Philips Semiconductors
Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
SAA7785
D23
D22
D21
D20
D19
D18
D17
D16
SONGBASE[23:16] POR Value 0 0 0 0 0 0 0 0
D15
D14
D13
D12
D11
D10
D9
D8
SONGBASE[15:8] POR Value 0 0 0 0 0 0 0 0
D7 SONG BASE[7] POR Value 0
D6 R 0
D5 R 0
D4 R 0
D3 R 0
D2 R 0
D1 R 0
D0 IO 1
Bit 31:7
Name SONGBASE
R/W RW
Function Thunderbird non-legacy device base address register. This register supplies the I/O base address for the non-legacy I/O devices within the SSA7785 ThunderBird AvengerTM chip. Reserved. These bits are reserved a must always return a zero for plug and play. I/O flag. This read only bit indicates that this is an I/O range.
6:1 0
R IO
RO RO
SSA7785 ThunderBird AvengerTM CFG Space 0 Legacy Base Address Registers The SSA7785 ThunderBird AvengerTM contains three legacy I/O base registers in configuration space 0. These legacy devices are the Sound Blaster register, the AdLib registers and the MIDI interface registers. They are described in detail in the next three tables. TABLE 21 PCI CFG 0 Offset 14h POR Value 0 0 0 Sound Blaster Base Address- SBBASE (RW/RO) D31 D30 D29 D28 D27 D26 D25 D24
SBBASE[31:24] 0 0 0 0 0
D23
D22
D21
D20
D19
D18
D17
D16
SBBASE[23:16] POR Value 0 0 0 0 0 0 0 0
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Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
SAA7785
D15
D14
D13
D12
D11
D10
D9
D8
SBBASE[15:8] POR Value 0 0 0 0 0 0 0 0
D7
D6
D5
D4
D3 R
D2 R 0
D1 R 0
D0 IO 1
SBBASE[7:4] POR Value 0 0 0 0
0
Bit 31:4
Name SBBASE
R/W RW
Function Sound Blaster programmable base address. The address should be on a 16 byte boundary. For reference, the Sound Blaster legacy base addresses are 220h and 240h. Note that accesses from the AdLib base address are mapped into a subset of the SoundBlaster registers. Reserved. These bits are reserved and always return zeros for plug and play. I/O flag. This read only bit indicates that this is an I/O range.
3:1 0
R IO
RO RO
TABLE 22 PCI CFG 0 Offset 18h POR Value
MIDI Base Address- MDBASE (RW/RO) D31 D30 D29 D28 D27 D26 D25 D24
MDBASE[31:24] 0 0 0 0 0 0 0 0
D23
D22
D21
D20
D19
D18
D17
D16
MDBASE[23:16] POR Value 0 0 0 0 0 0 0 0
D15
D14
D13
D12
D11
D10
D9
D8
MDBASE[15:8] POR Value 0 0 0 0 0 0 0 0
D7
D6
D5
D4
D3
D2
D1 R
D0 IO 1
MDBASE[7:2] POR Value 0 0 0 0 0 0
0
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Philips Semiconductors
Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
SAA7785
Bit 31:2
Name MDBASE
R/W RW
Function MIDI port programmable base address. The address should be on a double word boundary. For reference the MIDI port legacy base addresses are 220h, 230h, 240h, 250h, 300h, 320h, 330h, 332h, 334h, 336h, 340h, and 360h. Reserved. This bit is reserved a must always return a zero for plug and play. I/O flag. This read only bit indicates that this is an I/O range.
1 0
R IO
RO RO
TABLE 23 PCI CFG 0 Offset 1Ch POR Value
ADLIB Base Address Register - ALBASE (RW/RO) D31 D30 D29 D28 D27 D26 D25 D24
ALBASE[31:24] 0 0 0 0 0 0 0 0
D23
D22
D21
D20
D19
D18
D17
D16
ALBASE[23:16] POR Value 0 0 0 0 0 0 0 0
D15
D14
D13
D12
D11
D10
D9
D8
ALBASE[15:8] POR Value 0 0 0 0 0 0 0 0
D7
D6
D5 ALBASE[7:3]
D4
D3
D2 R
D1 R 0
D0 IO 1
POR Value
0
0
0
0
0
0
Bit 31:3
Name ALBASE
R/W RW
Function AdLib registers programmable base address. The address should be on a quad word (64 bit) boundary. For reference, the AdLib legacy base address is at 388h and maps into a subset of the Sound Blaster registers. Reserved. These bits are reserved and always return zeros for plug and play. I/O flag. This read only bit indicates that this is an I/O range.
2:1 0
R IO
RO RO
TABLE 24 PCI CFG 0 Offset 2Ch
Subsystem Vendor ID - SUBVENID (RO) D15 D14 D13 D12 D11 D10 D9 D8
SUBVEN_ID[15:8]
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Philips Semiconductors
Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
0 0 0 1 0 0 0
SAA7785
POR Value
0
D7
D6
D5
D4
D3
D2
D1
D0
SUBVEN_ID[7:0] POR Value 0 0 0 0 0 1 0 0
Bit 15:0
Name SUBVEN_ID
R/W RO
Function Subsystem Vendor ID. The Subsystem Vendor ID register allows the manufacturer to uniquely identify their board since more than one board OEM may use the SSA7785 ThunderBird AvengerTM chip. The Subsystem Vendor ID register is loaded by an external EEPROM via the Serial Configuration Port after reset and before any access to the PCI configuration header. The PCI target logic should force a retry if the Subsystem Vendor ID register has not completed loading. The Subsystem Vendor ID is read only to the PCI interface. If no external EEPROM is present, then the default Subsystem Vendor ID is 1004h, that of Philips Semiconductors (VLSI).
TABLE 25 PCI CFG 0 Offset 2Eh POR Value
Subsystem ID - SUBSYSID (RO) D15 D14 D13 D12 D11 D10 D9 D8
SUBSYS_ID[15:8] 0 0 0 0 0 0 1 1
D7
D6
D5
D4
D3
D2
D1
D0
SUBSYS_ID[7:0] POR Value 0 0 0 0 0 1 0 0
Bit 15:0
Name SUBSYS_ID
R/W RO
Function Subsystem ID. The Subsystem ID register allows the manufacturer to uniquely identify their board since more than one board OEM may use the SSA7785 ThunderBird AvengerTM chip. The Subsystem ID register is loaded by an external EEPROM via the Serial Configuration Port after reset and before any access to the PCI configuration header. The PCI target logic should force a retry if the Subsystem ID register has not completed loading. The Subsystem ID is read only to the PCI interface. If no external EEPROM is present, then the default Subsystem ID is 0304h, identical to the SSA7785 ThunderBird AvengerTM function 0 Device ID.
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Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
TABLE 26 PCI CFG 0 Offset 3Ch POR Value 0 0 0 Interrupt Line Register - INTLINE (RW) D7 D6 D5 D4 D3 D2 D1
SAA7785
D0
INTLINE[7:0] 0 0 0 0 0
Bit 7:0
Name INTLINE
R/W RW
Function Interrupt Line. The Interrupt Line register is an eight bit register used to communicate interrupt line routing information. The value in this register tells which input of the system interrupt controller(s) the SSA7785 ThunderBird AvengerTM Device's interrupt pin is connected to. If serial interrupts are enabled (COMARCH0 Register IRQSER=1) then the INT_LINE register will be read only and will have the value of all 1's. If Serial Interrupts are disabled (IRQSER=0) then the INT_LINE register will be readable/writable.
TABLE 27 PCI CFG 0 Offset 3Dh POR Value
Interrupt Pin Register - INTPIN (RO) D7 D6 D5 D4 D3 D2 D1 D0
INTPIN[7:0] 0 0 0 0 0 0 0 1
Bit 7:0
Name INTPIN
R/W RO
Function Interrupt Pin. The interrupt pin register tells which interrupt the SSA7785 ThunderBird AvengerTM device uses. If serial interrupts are enabled (COMARCH0 Register IRQSER=1) then the INT_PIN register will have the read only value of all 0's implying that the SSA7785 ThunderBird AvengerTM device does not use any of the PCI Interrupt pins. If Serial Interrupts are disabled (IRQSER=0) then the INT_PIN register will have the read only value of 01h implying that the SSA7785 ThunderBird AvengerTM device uses INT A interrupt pin.
TABLE 28 PCI CFG 0 Offset 3Eh POR Value
MIN_GNT Register - MINGNT (RO) D7 D6 D5 D4 D3 D2 D1 D0
MINGNT[7:0] 0 0 0 0 1 0 0 1
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Philips Semiconductors
Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
SAA7785
Bit 7:0
Name MINGNT
R/W RO
Function Minimum grant specifies how long of a burst period the device needs assuming a clock speed of 33MHz. Since the SSA7785 ThunderBird AvengerTM, function 0, will burst a maximum of 64 double words, therefore requiring about 75 33MHz clocks or 2.25 microseconds. The time units specified are in 0.25 microsecond increments.
TABLE 29 PCI CFG 0 Offset 3Fh POR Value
MAX_LAT Register - MAXLAT (RO) D7 D6 D5 D4 D3 D2 D1 D0
MAXLAT[7:0] 0 0 1 0 1 0 0 0
Bit 7:0
Name MAXLAT
R/W RO
Function Maximum latency specifies how often a device needs to gain access to the PCI bus. The SSA7785 ThunderBird AvengerTM, function 0, should only request the bus a a maximum of every 10 microseconds. The MAXLAT value is computed using the same parameters as the MINGNT.
SSA7785 ThunderBird AvengerTM CFG Space 0 DMA Base Registers This section will describe the PCI configuration registers that provide functions such as base address remapping and the like. These registers reside within the PCI interface. TABLE 30 PCI CFG 0 Offset 40h POR Value 0 0 0 DMA Channel A Base Address Register - DMAABASE (RW) D15 D14 D13 D12 D11 D10 D9 D8
DMAABASE[15:8] 0 0 0 0 0
D7 DMAA BASE[7] POR Value 0
D6 R 0
D5
D4
D3 R 0
D2
D1
D0 DDMAA EN 0
DMAABASE[5:4] 0 0
XFRSIZ[1:0] 1 0
Bit 15:7 6
Name DMAABASE R
R/W RW RO
Function DMA channel A programmable base address, bits 15:7. Reserved. This bit must always be zero.
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Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
SAA7785
Bit 5:4
Name DMAABASE
R/W RW
Function DMA channel A programmable base address, bits 5:4. These bits select a channel number for this channel. In LAM DMAABASE[5:4] select the channel number that this DMA represents, it should be different than DMABBASE[5:4]. Reserved. This bit must always be zero. DMA transfer size. 00 = reserved 10 = double word 11 = reserved 01 = reserved
3 2:1
R XFRSIZ
RO RW
0
DDMAAEN
RW
DDMA channel A enable. This DDMA channel is enabled when this bit is set to a one.
TABLE 31 PCI CFG 0 Offset 42h POR Value
DMA Channel B Base Address Register - DMABBASE (RW) D31 D30 D29 D28 D27 D26 D25 D24
DMABBASE[15:8] 0 0 0 0 0 0 0 0
D23 DMAB BASE[7] POR Value 0
D22 R 0
D21
D20
D19 R 0
D18 R 0
D17 R 0
D16 DDMAB EN 0
DMABBASE[5:4] 0 0
Bit 15:7
Name DMABBASE
R/W RW
Function DMA channel B programmable base address. Normally this base is set the same as DMA channel A except for DMABBASE[5:4] which select the channel number. This is a requirement of some PC chipsets, future chipsets may eliminate this requirement. In LAM DMABBASE[5:4] select the channel number that this DMA represents, it should be different than DMAABASE[5:4]. Reserved. This bit must always be zero. DMA channel B programmable base address, bits 5:4. These bits select a channel number for this channel. In LAM DMABBASE[5:4] select the channel number that this DMA represents, it should be different than DMAABASE[5:4]. Reserved. These bits must always be zeros. DMA channel B enable. This DDMA channel is enabled when this bit is set to a one.
6 5:4
R DMABBASE
RO RW
3:1 0
R DDMABEN
RO RW
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Philips Semiconductors
Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
TABLE 32 PCI CFG 0 Offset 58h POR Value 0 0 0 0 0 0 0 Miscellaneous Configuration Register - MSCCFG (RO/RW) D7 D6 D5 RDY_EN D4 CFGCLK D3 BHEN D2 D1
SAA7785
D0 PCPCI _EN 0
ASYMCLK[1:0]
PCCH[1:0]
Bit 7:6 5
Name ASYMCLK RDY_EN
R/W RW RW
Function Asymmetrical Clock Select. These bits program the duty cycle for the input for the two phase DSP clock generator. Music registers ready enable. When set, the music registers will cause the PCI interface to retry when either of the music registers (music0 or music1) are full. Serial Configuration Port Clock Select. This bit selects the clock output to the Configuration Serial Port. 0 = Ouput a 400 KHz clock. Incoming data will be synchronized to this clock. 1 = Output the PCI clock.
4
CFGCLK
RW
3 2:1 0
BHEN PCCH PCPCI_EN
RW RW RW
Bus Hog Fix Enable. These two bits are the encoded channel number that the soundblaster will be on in the PC/PCI mode and are valid only when the PC/PCI mode is enabled. PC/PCI mode enable bit. This bit, when set = 1, will enable the PC/PCI sideband signals for the Soundblaster legacy mode.
PCI Configuration Space 1 The following table is a summary of all the PCI configuration space registers. The registers that are block-mates with the PCI interface (offset 00h - 3Ch) will be detailed following SSA7785 ThunderBird AvengerTM. The remainder of the registers will be detailed with the blocks they control. This register space is for the joystick. TABLE 33 Byte 3 PCI Configuration Space 1 Register Map Byte 2
Device ID Status Class Code BIST Header Type Master Latency Timer GMBASE Reserved Subsystem ID Reserved Max_Lat Min_Gnt Reserved Interrupt Pin Interrupt Line Subsystem Vendor ID
Byte 1
Byte 0
Vendor ID Command Revision ID Cache Line Size
Offset
00h 04h 08h 0Ch 10h 14-2B 2Ch 30-3Bh 3Ch 40-6Bh
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Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
Reserved Reserved Reserved Reserved GAMECFG0
SAA7785
6Ch 70-FFh
TABLE 34 PCI CFG 1 Offset 00h POR Value
Vendor ID Register - VENDOR_ID (RO) D15 D14 D13 D12 D11 D10 D9 D8
VENDOR_ID[15:8] 0 0 0 1 0 0 0 0
D7
D6
D5
D4
D3
D2
D1
D0
VENDOR_ID[7:0] POR Value 0 0 0 0 0 1 0 0
Bit 15:0
Name VENDOR_ID
R/W RO
Function The PCI Vendor ID for Philips Semiconductors (VLSI) is 1004h.
TABLE 35 PCI CFG 1 Offset 02h POR Value
Device ID Register - DEVICE_ID (RO) D15 D14 D13 D12 D11 D10 D9 D8
DEVICE_ID[15:8] 0 0 0 0 0 0 1 1
D7
D6
D5
D4
D3
D2
D1
D0
DEVICE_ID[7:0] POR Value 0 0 0 0 0 1 0 1
Bit 15:0
Name DEVICE_ID
R/W RO
Function The Device ID for the SSA7785 ThunderBird AvengerTM, function 1 is 0305h.
TABLE 36 PCI CFG 1 Offset 04h POR Value
Command Register - COMMAND (RO/RW) D15 R 0 D14 R 0 D13 R 0 D12 R 0 D11 R 0 D10 R 0 D9 FBACK_ ENB 0 D8 SERR_R ESP 0
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Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
SAA7785
D7 STEPPING POR Value 0
D6 PERR_ RESP 0
D5 SNOOP_ ENB 0
D4 MEM_ INV_EN 0
D3 SPEC_ CNTL 0
D2 MAST_ CNTL 0
D1 MEM_ CNTL 0
D0 IO_ CNTL 0
Bit 15:10 9 R
Name
R/W RO RO
Function Reserved. These bits always return zero. Fast Back-to-Back Enable: the SSA7785 ThunderBird AvengerTM, function 1 does not support fast back to back master cycles therefore this bit always returns a zero. System Error Response: When set to 1, the SSA7785 ThunderBird AvengerTM, function 1 responds to detected PCI bus address parity errors by asserting SERR#. When 0, the SSA7785 ThunderBird AvengerTM ignores these errors. Address / Data Stepping: Always returns 0. Parity Error Response: When set to 1, the SSA7785 ThunderBird AvengerTM, function 1 responds to detected PCI bus data parity errors by asserting PERR#. When 0, the SSA7785 ThunderBird AvengerTM ignores PCI bus data parity errors. VGA Snoop Enable. The SSA7785 ThunderBird AvengerTM, function 1 does not support VGA snoop enable, therefor this bit always returns a zero. Memory Write and Invalidate Enable: Always returns 0. Special Cycle Control: Controls the devices ability to respond to Special Cycle Operations. A value of 0 causes the SSA7785 ThunderBird AvengerTM, function 1 to ignore all Special Cycles. Master Control: The SSA7785 ThunderBird AvengerTM, function 1 does not have any master functions. Memory Response Control: The SSA7785 ThunderBird AvengerTM, function 1 does not support target memory cycles therefore this bit always returns a zero. I/O Response Control: Controls the SSA7785 ThunderBird AvengerTM, function 1's response to I/O space. A value of 0 disables the device response. A value of 1 allows the device to respond to I/O space accesses.
FBACK_ENB
8
SERR_RESP
RW
7 6
STEPPING PERR_RESP
RO RW
5 4 3
SNOOP_ENB MEM_INV_EN SPEC_CNTL
RO RO RO
2 1
MAST_CNTL MEM_CNTL
RO RO
0
IO_CNTL
RW
TABLE 37 PCI CFG 1 Offset 06h POR Value
Status Register - STATUS (RO/RW) D15 R_PERR 0 D14 S_SERR 0 D13 SM_ ABORT 0 D12 RT_ ABORT 0 D11 ST_ ABORT 0 0 1 0 D10 D9 D8 S_PERR
DEVSEL_TMG
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Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
SAA7785
D7 F_ BK2BK POR Value 1
D6 UDF 0
D5 MHz66 0
D4 R 0
D3 R 0
D2 R 0
D1 R 0
D0 R 0
Bit 15
Name R_PERR
R/W RC
Function Received Parity Error: When set to 1, this bit indicates that the SSA7785 ThunderBird AvengerTM, function 1 has detected a PCI bus parity error at least once since this bit was last reset. Signalled System Error: When set to 1, this bit indicates that the SSA7785 ThunderBird AvengerTM, function 1 has reported a system error on the SERR# signal at least once since this bit was last reset. Signalled Master Abort: The SSA7785 ThunderBird AvengerTM, function 1, does not act as a master. Received Target Abort: The SSA7785 ThunderBird AvengerTM, function 1 does not act as a master. Signalled Target Abort: When set to 1, this bit indicates that the SSA7785 ThunderBird AvengerTM, function 1 has signalled a target abort at least once since this bit was last reset. DEVSEL Timing: This field indicates the timing of the DEVSEL output (when a PCI master is accessing a SSA7785 ThunderBird AvengerTM, function 1 resource). It always returns 01 (Bin). 00 = Fast 01 = Medium (Default Timing) 10 = Slow
14
S_SERR
RC
13 12 11
SM_ABORT RT_ABORT ST_ABORT
RO RO RC
10:9
DEVSEL_TM G
RO
8 7 6 5 4:0
S_PERR F_BK2BK UDF MHz66 R
RO RO RO RO RO
Signalled Parity Error: The SSA7785 ThunderBird AvengerTM, function 1, does not act as a bus master. Always returns 1 to indicate support of fast back to back cycles when the SSA7785 ThunderBird AvengerTM, function 1 is the target. User Definable Features. Always returns 0. 66 MHz Capable. Always returns 0. Reserved. These bits always return zero.
Note: An RC indicates that this bit can be reset to 0 by writing a 1. Writing a zero leaves this bit unchanged. TABLE 38 PCI CFG 1 Offset 08h POR Value 0 0 0 Revision ID Register - REVISION (RO) D7 D6 D5 D4 D3 D2 D1 D0
REVISION_ID[7:0] 0 0 0 0 0
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Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
SAA7785
Bit 7:0
Name REVISION_ID
R/W RO
Function The current revision ID for the SSA7785 ThunderBird AvengerTM joystick.
TABLE 39 PCI CFG 1 Offset 09h POR Value
Class Code Register - CLASS (RO) D23 D22 D21 D20 D19 D18 D17 D16
BASE_CLASS[7:0] 0 0 0 0 1 0 0 1
D15
D14
D13
D12
D11
D10
D9
D8
SUB_CLASS[7:0] POR Value 1 0 0 0 0 0 0 0
D7
D6
D5
D4
D3
D2
D1
D0
PGM_IFACE[7:0] POR Value 0 0 0 0 0 0 0 0
Bit 23:16 15:8 7:0
Name BASE_CLASS SUB_CLASS PGM_IFACE
R/W RO RO RO
Function The base class of 09h describes an input device. The sub class of 80h describes a "other" input controller. Device generic function identification.
TABLE 40 PCI CFG 1 Offset 0Ch POR Value
CACHELINE Size Register - CACHELINE (RO) D7 D6 D5 D4 D3 D2 D1 D0
CACHELINE[7:0] 0 0 0 0 0 0 0 0
Bit 7:0
Name CACHELINE
R/W RO
Function Reserved for cache line size indicator.
TABLE 41 PCI CFG 1 Offset 0Dh
Master Latency Timer Register - LATIME (RW) D7 D6 D5 D4 D3 D2 D1 D0
LATIME[7:0]
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Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
SAA7785
PCI CFG 1 POR Value
D7 0
D6 0
D5 0
D4 0
D3 0
D2 0
D1 0
D0 0
Bit 7:0
Name LATIME
R/W RO
Function The primary bus latency timer specifies the number of primary clocks that the primary master may consume. It is set to zero since the joystick is a target only.
TABLE 42 PCI CFG 1 Offset 0Eh POR Value
Header Type Register - HEADER (RO) D7 MULTI_ FN 1 0 0 0 0 0 0 0 D6 D5 D4 D3 HEADER[6:0] D2 D1 D0
Bit 7 6:0
Name MULTI_FN HEADER
R/W RO RO
Function For the SSA7785 ThunderBird AvengerTM, function 1, this bit has no meaning. Header Type. A 00h indicates this device is not a PCI-to-PCI bridge.
TABLE 43 PCI CFG 1 Offset 0Fh POR Value
BIST Register - BIST (RO) D7 BIST 0 D6 START 0 D5 R 0 D4 R 0 0 0 D3 D2 D1 D0
CODE[3:0] 0 0
Bit 7 6
Name BIST START
R/W RO RO
Function BIST capable. BIST is not supported in the SSA7785 ThunderBird AvengerTM, function 1 at this revision. If BIST capable, this bit will start the BIST. Writing a 1 will start the test and the BIST should write this bit to a zero when complete. Software should fail the device if the BIST is not complete after 2 seconds. Reserved. These bits always return zero. Completion Code. A value of zero means the device has passed its test. Non-zero values means the device has failed using device specific failure codes.
5:4 3:0
R CODE
RO RO
SSA7785 ThunderBird AvengerTM CFG Space 1 Legacy Base Address Registers
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Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
SAA7785
The SSA7785 ThunderBird AvengerTM, contains one legacy I/O base registers in configuration space 1. The joystick is the sole legacy I/O base address register and is documented here. TABLE 44 PCI CFG 1 Offset 10h POR Value 0 0 0 Game Port(JOYSTICK) Base Address - GMBASE (RW/RO) D31 D30 D29 D28 D27 D26 D25 D24
GMBASE[31:24] 0 0 0 0 0
D23
D22
D21
D20
D19
D18
D17
D16
GMBASE[23:16] POR Value 0 0 0 0 0 0 0 0
D15
D14
D13
D12
D11
D10
D9
D8
GMBASE[15:8] POR Value 0 0 0 0 0 0 0 0
D7
D6
D5 GMBASE[7:3]
D4
D3
D2 R
D1 R 0
D0 IO 1
POR Value
0
0
0
0
0
0
Bit 31:3 2:1 0
Name GMBASE R IO
R/W RW RO RO
Function Game port programmable base address. The address should be on a 8 byte boundary. For reference, the game port legacy base address is 201h. Reserved. These bits are reserved and always return zeros for plug and play. I/O flag. This read only bit indicates that this is an I/O range.
TABLE 45 PCI CFG 1 Offset 2Ch POR Value
Subsystem Vendor ID - SUBVENID (RO) D15 D14 D13 D12 D11 D10 D9 D8
SUBVEN_ID[15:8] 0 0 0 1 0 0 0 0
D7
D6
D5
D4
D3
D2
D1
D0
SUBVEN_ID[7:0] POR Value 0 0 0 0 0 1 0 0
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Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
SAA7785
Bit 15:0
Name SUBVEN_ID
R/W RO
Function Subsystem Vendor ID. The Subsystem Vendor ID register allows the manufacturer to uniquely identify their board since more than one board OEM may use the SSA7785 ThunderBird AvengerTM chip. The Subsystem Vendor ID register is loaded by an external EEPROM via the Serial Configuration Port after reset and before any access to the PCI configuration header. The PCI target logic should force a retry if the Subsystem Vendor ID register has not completed loading. The Subsystem Vendor ID is read only to the PCI interface. If no external EEPROM is present, then the default Subsystem Vendor ID is 1004h, that of Philips Semiconductors (VLSI).
TABLE 46 PCI CFG 1 Offset 2Eh POR Value
Subsystem ID - SUBSYSID (RO) D15 D14 D13 D12 D11 D10 D9 D8
SUBSYS_ID[15:8] 0 0 0 0 0 0 1 1
D7
D6
D5
D4
D3
D2
D1
D0
SUBSYS_ID[7:0] POR Value 0 0 0 0 0 1 0 1
Bit 15:0
Name SUBSYS_ID
R/W RO
Function Subsystem ID. The Subsystem ID register allows the manufacturer to uniquely identify their board since more than one board OEM may use the SSA7785 ThunderBird AvengerTM chip. The Subsystem ID register is loaded by an external EEPROM via the Serial Configuration Port after reset and before any access to the PCI configuration header. The PCI target logic should force a retry if the Subsystem ID register has not completed loading. The Subsystem ID is read only to the PCI interface. If no external EEPROM is present, then the default Subsystem ID is 0305h, identical to the SSA7785 ThunderBird AvengerTM function 1 Device ID.
TABLE 47 PCI CFG 1 Offset 3Ch POR Value
Interrupt Line Register - INTLINE (RO) D7 D6 D5 D4 D3 D2 D1 D0
INTLINE[7:0] 0 0 0 0 0 0 0 0
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Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
SAA7785
Bit 7:0
Name INTLINE
R/W RO
Function Interrupt Line. The Interrupt Line register is an eight bit register used to communicate interrupt line routing information. The value in this register tells which input of the system interrupt controller(s) the SSA7785 ThunderBird AvengerTM Device's interrupt pin is connected to. It is set to 00h to use function 0's interrupt line. There is no legacy interrupt support for function 1.
TABLE 48 PCI CFG 1 Offset 3Dh POR Value
Interrupt Pin Register - INTPIN (RO) D7 D6 D5 D4 D3 D2 D1 D0
INTPIN[7:0] 0 0 0 0 0 0 0 0
Bit 7:0
Name INTPIN
R/W RO
Function Interrupt Pin. The interrupt pin register tells which interrupt the SSA7785 ThunderBird AvengerTM device uses. The read only value of 00h implies that the SSA7785 ThunderBird AvengerTM device shares the INT A interrupt pin with function 0. There is no legacy interrupt support for function 1.
TABLE 49 PCI CFG 1 Offset 3Eh POR Value
MIN_GNT Register - MINGNT (RO) D7 D6 D5 D4 D3 D2 D1 D0
MINGNT[7:0] 0 0 0 0 0 0 0 0
Bit 7:0
Name MINGNT
R/W RO
Function Minimum grant specifies how long of a burst period the device needs assuming a clock speed of 33MHz. Since the SSA7785 ThunderBird AvengerTM, function 1, is a target only, this register is read only and set to zero.
TABLE 50 PCI CFG 1 Offset 3Fh POR Value
MAX_LAT Register - MAXLAT (RO) D7 D6 D5 D4 D3 D2 D1 D0
MAXLAT[7:0] 0 0 0 0 0 0 0 0
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Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
SAA7785
Bit 7:0
Name MAXLAT
R/W RO
Function Maximum latency specifies how often a device needs to gain access to the PCI bus. The SSA7785 ThunderBird AvengerTM, function 1, is a target only, this register is read only and set to zero.
PCI Configuration Space 2 The following table is a summary of all the PCI configuration space registers. The registers that are block-mates with the PCI interface (offset 00h - 3Ch) will be detailed following SSA7785 ThunderBird AvengerTM. The remainder of the registers will be detailed with the blocks they control. This register space is for the 16650 UART. TABLE 51 Byte 3 PCI Configuration Space 2 Register Map Byte 2
Device ID Status Class Code BIST Header Type Master Latency Timer UARTBASE Reserved Subsystem ID Reserved Max_Lat Reserved Reserved Min_Gnt Reserved Reserved Reserved Interrupt Pin Reserved Reserved Interrupt Line UARTCFG0 SFCR Subsystem Vendor ID
Byte 1
Byte 0
Vendor ID Command Revision ID Cache Line Size
Offset
00h 04h 08h 0Ch 10-13h 14-2B 2Ch 30-3Bh 3Ch 40h 44h 48-FFh
TABLE 52 PCI CFG 2 Offset 00h POR Value
Vendor ID Register - VENDOR_ID (RO) D15 D14 D13 D12 D11 D10 D9 D8
VENDOR_ID[15:8] 0 0 0 1 0 0 0 0
D7
D6
D5
D4
D3
D2
D1
D0
VENDOR_ID[7:0] POR Value 0 0 0 0 0 1 0 0
Bit 15:0
Name VENDOR_ID
R/W RO
Function The PCI Vendor ID for Philips Semiconductors (VLSI) is 1004h.
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ThunderBird AvengerTM PCI Audio Accelerator
TABLE 53 PCI CFG 2 Offset 02h POR Value 0 0 0 Device ID Register - DEVICE_ID (RO) D15 D14 D13 D12 D11 D10 D9
SAA7785
D8
DEVICE_ID[15:8] 0 0 0 1 1
D7
D6
D5
D4
D3
D2
D1
D0
DEVICE_ID[7:0] POR Value 0 0 0 0 0 1 1 0
Bit 15:0
Name DEVICE_ID
R/W RO
Function The Device ID for the SSA7785 ThunderBird AvengerTM, function 2 is 0306h.
TABLE 54 PCI CFG 2 Offset 04h POR Value
Command Register - COMMAND (RO/RW) D15 R 0 D14 R 0 D13 R 0 D12 R 0 D11 R 0 D10 R 0 D9 FBACK_ ENB 0 D8 SERR_R ESP 0
D7 STEPPING POR Value 0
D6 PERR_ RESP 0
D5 SNOOP_ ENB 0
D4 MEM_ INV_EN 0
D3 SPEC_ CNTL 0
D2 MAST_ CNTL 0
D1 MEM_ CNTL 0
D0 IO_ CNTL 0
Bit 15:10 9 R
Name
R/W RO RO
Function Reserved. These bits always return zero. Fast Back-to-Back Enable: the SSA7785 ThunderBird AvengerTM, function 2 does not support fast back to back master cycles therefore this bit always returns a zero. System Error Response: When set to 1, the SSA7785 ThunderBird AvengerTM, function 2 responds to detected PCI bus address parity errors by asserting SERR#. When 0, the SSA7785 ThunderBird AvengerTM ignores these errors. Address / Data Stepping: Always returns 0. Parity Error Response: When set to 1, the SSA7785 ThunderBird AvengerTM, function 2 responds to detected PCI bus data parity errors by asserting PERR#. When 0, the SSA7785 ThunderBird AvengerTM ignores PCI bus data parity errors.
FBACK_ENB
8
SERR_RESP
RW
7 6
STEPPING PERR_RESP
RO RW
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Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
SAA7785
Bit 5 4 3
Name SNOOP_ENB MEM_INV_EN SPEC_CNTL
R/W RO RO RO
Function VGA Snoop Enable. The SSA7785 ThunderBird AvengerTM, function 2 does not support VGA snoop enable, therefor this bit always returns a zero. Memory Write and Invalidate Enable: Always returns 0. Special Cycle Control: Controls the devices ability to respond to Special Cycle Operations. A value of 0 causes the SSA7785 ThunderBird AvengerTM, function 2 to ignore all Special Cycles. Master Control: The SSA7785 ThunderBird AvengerTM, function 2 does not have any master functions. Memory Response Control: The SSA7785 ThunderBird AvengerTM, function 2 does not support target memory cycles therefore this bit always returns a zero. I/O Response Control: Controls the SSA7785 ThunderBird AvengerTM, function 2's response to I/O space. A value of 0 disables the device response. A value of 1 allows the device to respond to I/O space accesses.
2 1
MAST_CNTL MEM_CNTL
RO RO
0
IO_CNTL
RW
TABLE 55 PCI CFG 2 Offset 06h POR Value
Status Register - STATUS (RO/RW) D15 R_PERR 0 D14 S_SERR 0 D13 SM_ ABORT 0 D12 RT_ ABORT 0 D11 ST_ ABORT 0 0 1 0 D10 D9 D8 S_PERR
DEVSEL_TMG
D7 F_ BK2BK POR Value 1
D6 UDF 0
D5 MHz66 0
D4 R 0
D3 R 0
D2 R 0
D1 R 0
D0 R 0
Bit 15
Name R_PERR
R/W RC
Function Received Parity Error: When set to 1, this bit indicates that the SSA7785 ThunderBird AvengerTM, function 2 has detected a PCI bus parity error at least once since this bit was last reset. Signalled System Error: When set to 1, this bit indicates that the SSA7785 ThunderBird AvengerTM, function 2 has reported a system error on the SERR# signal at least once since this bit was last reset. Signalled Master Abort: The SSA7785 ThunderBird AvengerTM, function 2, does not act as a master. Received Target Abort: The SSA7785 ThunderBird AvengerTM, function 2 does not act as a master.
14
S_SERR
RC
13 12
SM_ABORT RT_ABORT
RO RO
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Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
SAA7785
Bit 11
Name ST_ABORT
R/W RC
Function Signalled Target Abort: When set to 1, this bit indicates that the SSA7785 ThunderBird AvengerTM, function 2 has signalled a target abort at least once since this bit was last reset. DEVSEL Timing: This field indicates the timing of the DEVSEL output (when a PCI master is accessing a SSA7785 ThunderBird AvengerTM resource). It always returns 01 (Bin). 00 = Fast 01 = Medium (Default Timing) 10 = Slow
10:9
DEVSEL_TM G
RO
8 7 6 5 4:0
S_PERR F_BK2BK UDF MHz66 R
RO RO RO RO RO
Signalled Parity Error: The SSA7785 ThunderBird AvengerTM, function 2, does not act as a bus master. Always returns 1 to indicate support of fast back to back cycles when the SSA7785 ThunderBird AvengerTM, function 2 is the target. User Definable Features. Always returns 0. 66 MHz Capable. Always returns 0. Reserved. These bits always return zero.
Note: An RC indicates that this bit can be reset to 0 by writing a 1. Writing a zero leaves this bit unchanged. TABLE 56 PCI CFG 2 Offset 08h POR Value 0 0 0 Revision ID Register - REVISION (RO) D7 D6 D5 D4 D3 D2 D1 D0
REVISION_ID[7:0] 0 0 0 0 0
Bit 7:0
Name REVISION_ID
R/W RO
Function The current revision ID for the SSA7785 ThunderBird AvengerTM, function 2 joystick..
TABLE 57 PCI CFG 2 Offset 09h POR Value
Class Code Register - CLASS (RO) D23 D22 D21 D20 D19 D18 D17 D16
BASE_CLASS[7:0] 0 0 0 0 0 1 1 1
D15
D14
D13
D12
D11
D10
D9
D8
SUB_CLASS[7:0] POR Value 0 0 0 0 0 0 0 0
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Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
SAA7785
PCI CFG 2
D23 D7
D22 D6
D21 D5
D20 D4
D19 D3
D18 D2
D17 D1
D16 D0
PGM_IFACE[7:0] POR Value 0 0 0 0 0 0 1 0
Bit 23:16 15:8 7:0
Name BASE_CLASS SUB_CLASS PGM_IFACE
R/W RO RO RO
Function The base class of 07h describes simple communication devices. The sub class of 00h describes serial controllers. The interface of 02h details a 16550 compatible serial controller.
TABLE 58 PCI CFG 2 Offset 0Ch POR Value
CACHELINE Size Register - CACHELINE (RO) D7 D6 D5 D4 D3 D2 D1 D0
CACHELINE[7:0] 0 0 0 0 0 0 0 0
Bit 7:0
Name CACHELINE
R/W RO
Function Reserved for cache line size indicator.
TABLE 59 PCI CFG 2 Offset 0Dh POR Value
Master Latency Timer Register - LATIME (RW) D7 D6 D5 D4 D3 D2 D1 D0
LATIME[7:0] 0 0 0 0 0 0 0 0
Bit 7:0
Name LATIME
R/W RO
Function The primary bus latency timer specifies the number of primary clocks that the primary master may consume. It is set to zero since the 16650 UART is a target only.
TABLE 60 PCI CFG 2 Offset 0Eh POR Value
Header Type Register - HEADER (RO) D7 MULTI_ FN 1 0 0 0 0 0 0 0 D6 D5 D4 D3 HEADER[6:0] D2 D1 D0
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Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
SAA7785
Bit 7 6:0
Name MULTI_FN HEADER
R/W RO RO
Function For the SSA7785 ThunderBird AvengerTM, function 2, this bit has no meaning. Header Type. A 00h indicates this device is not a PCI-to-PCI bridge.
TABLE 61 PCI CFG 2 Offset 0Fh POR Value
BIST Register - BIST (RO) D7 BIST 0 D6 START 0 D5 R 0 D4 R 0 0 0 D3 D2 D1 D0
CODE[3:0] 0 0
Bit 7 6
Name BIST START
R/W RO RO
Function BIST capable. BIST is not supported in the SSA7785 ThunderBird AvengerTM, function 2 at this revision. If BIST capable, this bit will start the BIST. Writing a 1 will start the test and the BIST should write this bit to a zero when complete. Software should fail the device if the BIST is not complete after 2 seconds. Reserved. These bits always return zero. Completion Code. A value of zero means the device has passed its test. Non-zero values means the device has failed using device specific failure codes.
5:4 3:0
R CODE
RO RO
SSA7785 ThunderBird AvengerTM CFG Space 1 Legacy Base Address Registers The SSA7785 ThunderBird AvengerTM, contains one legacy I/O base registers in configuration space 1. The joystick is the sole legacy I/O base address register and is documented here. TABLE 62 PCI CFG 2 Offset 10h POR Value 0 0 0 16650 UART Base Address - UARTBASE (RW/RO) D31 D30 D29 D28 D27 D26 D25 D24
UARTBASE[31:24] 0 0 0 0 0
D23
D22
D21
D20
D19
D18
D17
D16
UARTBASE[23:16] POR Value 0 0 0 0 0 0 0 0
D15
D14
D13
D12
D11
D10
D9
D8
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ThunderBird AvengerTM PCI Audio Accelerator
UARTBASE[15:8] POR Value 0 0 0 0 0 0 0
SAA7785
0
D7
D6
D5 UARTBASE[7:3]
D4
D3
D2 R
D1 R 0
D0 IO 1
POR Value
0
0
0
0
0
0
Bit 31:3
Name UARTBASE R IO
R/W RW
Function 16650 UART base address. The address should be on a 8 byte boundary. For reference, 550 compatible UART legacy base addresses are 3E8h, 338h, 2E8h, 220h, 238h, 2E0h, 228h, 3F8h, and 2F8h. Reserved. These bits are reserved and always return zeros for plug and play. I/O flag. This read only bit indicates that this is an I/O range.
2:1 0
RO RO
TABLE 63 PCI CFG 2 Offset 2Ch POR Value
Subsystem Vendor ID - SUBVENID (RO) D15 D14 D13 D12 D11 D10 D9 D8
SUBVEN_ID[15:8] 0 0 0 1 0 0 0 0
D7
D6
D5
D4
D3
D2
D1
D0
SUBVEN_ID[7:0] POR Value 0 0 0 0 0 1 0 0
Bit 15:0
Name SUBVEN_ID
R/W RO
Function Subsystem Vendor ID. The Subsystem Vendor ID register allows the manufacturer to uniquely identify their board since more than one board OEM may use the SSA7785 ThunderBird AvengerTM chip. The Subsystem Vendor ID register is loaded by an external EEPROM via the Serial Configuration Port after reset and before any access to the PCI configuration header. The PCI target logic should force a retry if the Subsystem Vendor ID register has not completed loading. The Subsystem Vendor ID is read only to the PCI interface. If no external EEPROM is present, then the default Subsystem Vendor ID is 1004h, that of Philips Semiconductors (VLSI).
TABLE 64 PCI CFG 2
Subsystem ID - SUBSYSID (RO) D15 D14 D13 D12 D11 D10 D9 D8
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Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
SUBSYS_ID[15:8] 0 0 0 0 0 0 1
SAA7785
Offset 2Eh POR Value
1
D7
D6
D5
D4
D3
D2
D1
D0
SUBSYS_ID[7:0] POR Value 0 0 0 0 0 1 1 0
Bit 15:0
Name SUBSYS_ID
R/W RO
Function Subsystem ID. The Subsystem ID register allows the manufacturer to uniquely identify their board since more than one board OEM may use the SSA7785 ThunderBird AvengerTM chip. The Subsystem ID register is loaded by an external EEPROM via the Serial Configuration Port after reset and before any access to the PCI configuration header. The PCI target logic should force a retry if the Subsystem ID register has not completed loading. The Subsystem ID is read only to the PCI interface. If no external EEPROM is present, then the default Subsystem ID is 0306h, identical to the SSA7785 ThunderBird AvengerTM function 2 Device ID.
TABLE 65 PCI CFG 2 Offset 3Ch POR Value
Interrupt Line Register - INTLINE (RO) D7 D6 D5 D4 D3 D2 D1 D0
INTLINE[7:0] 0 0 0 0 0 0 0 0
Bit 7:0
Name INTLINE
R/W RO
Function Interrupt Line. The Interrupt Line register is an eight bit register used to communicate interrupt line routing information. The value in this register tells which input of the system interrupt controller(s) the SSA7785 ThunderBird AvengerTM Device's interrupt pin is connected to. It is set to 00h to use function 0's interrupt line. There is no legacy interrupt support for function 2.
TABLE 66 PCI CFG 2 Offset 3Dh POR Value
Interrupt Pin Register - INTPIN (RO) D7 D6 D5 D4 D3 D2 D1 D0
INTPIN[7:0] 0 0 0 0 0 0 0 0
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Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
SAA7785
Bit 7:0
Name INTPIN
R/W RO
Function Interrupt Pin. The interrupt pin register tells which interrupt the SSA7785 ThunderBird AvengerTM device uses. The read only value of 00h implies that the SSA7785 ThunderBird AvengerTM device shares the INT A interrupt pin with function 0. There is no legacy interrupt support for function 2.
TABLE 67 PCI CFG 2 Offset 3Eh POR Value
MIN_GNT Register - MINGNT (RO) D7 D6 D5 D4 D3 D2 D1 D0
MINGNT[7:0] 0 0 0 0 0 0 0 0
Bit 7:0
Name MINGNT
R/W RO
Function Minimum grant specifies how long of a burst period the device needs assuming a clock speed of 33MHz. Since the SSA7785 ThunderBird AvengerTM, function 2, is a target only, this register is read only and set to zero.
TABLE 68 PCI CFG 2 Offset 3Fh POR Value
MAX_LAT Register - MAXLAT (RO) D7 D6 D5 D4 D3 D2 D1 D0
MAXLAT[7:0] 0 0 0 0 0 0 0 0
Bit 7:0
Name MAXLAT
R/W RO
Function Maximum latency specifies how often a device needs to gain access to the PCI bus. The SSA7785 ThunderBird AvengerTM, function 2, is a target only, this register is read only and set to zero.
MULTIMEDIA TIMER
OVERVIEW The Multimedia Timer is a 20 bit counter with 840ns resolution for general purpose use under host software control. The timer subsystem consists of the 20-bit counter and I/O space registers. It takes three I/O cycles to read the complete value of the Timer since the device allows only byte accesses. The Multimedia Timer will get its time base by dividing down the CCLK clock. An interrupt and flag is provided to determine if the timer count has rolled over. The timer can either start from zero or be preloaded with a start value.
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Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
FIGURE 7 MULTIMEDIA TIMER BLOCK DIAGRAM
SAA7785
CCLK
CLOCK DIVIDE LOGIC
COUNTER CLOCK
CTL CTL INTERNAL PS BUS INTERFACE COUNT INTR 20 BIT - 1uS RESOLUTION UP COUNTER
PS BUS
INTERRUPT GENERATION LOGIC
MULTIMEDIA TIMER REGISTER DEFINITION There are five registers that control the multimedia timer. These registers are the timer control register, timer status, and timer count registers. The timer control register resides in PCI configuration space. The remainder of the timer registers are in I/O space. MULTIMEDIA TIMER PCI CONFIGURATION REGISTERS TABLE 69 PCI CFG 0 Offset 64h POR Value Bit 7:3 R Name TIMRCFG0 (RW/RO) - MULTIMEDIA TIMER CONFIG REGISTER 0 D7 R 0 R/W RO D6 R 0 D5 R 0 D4 R 0 D3 R 0 Function Reserved. These bits return zeros. D2 FSTCLK 0 D1 TMRRST 0 D0 R 0
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ThunderBird AvengerTM PCI Audio Accelerator
Bit 2 Name FSTCLK R/W RW Function
SAA7785
Fast Clock Enable. When set, the timer counter will use the CCLK clock instead of the 570 ns clock. This function will reduce the simulation and test time of the device. Timer Reset. When set, this bit holds the multimedia timer in reset. The multimedia timer is also reset by the system reset. Reserved. This bit returns a zero.
1 0
TMRRST R
RW RO
MULTIMEDIA TIMER I/O SPACE REGISTERS TABLE 70 SONGBASE Offset 00h POR Value Bit 7:4 3 R TPLD Name 0 R/W RO RW 0 0 0 0 Function Reserved. These bits return zeros. Timer Preload Indicator. When set, this indicates the timer will start counting from the values set in the timer count registers. When cleared, the timer will start counting from zero or its last value when stopped Timer Resume. When set, the timer will resume counting at the next 570 ns clock edge. When cleared, the timer will stop counting. Timer Interrupt. When asserted, the multimedia timer has flagged an interrupt when the timer has counted to zero. The timer will continue to count. Writing a one to this bit will clear the interrupt. Timer Interrupt Enable. When set, the multimedia timer will generate an interrupt. TMSTAT (RW/RO) - MULTIMEDIA TIMER STATUS REGISTER D7 R D6 R D5 R D4 R D3 TPLD D2 TRESUME 0 D1 TMINT 0 D0 TINTEN 0
2 1
TRESUME TMINT
RW WC
0
TINTEN
RW
MULTIMEDIA TIMER COUNT REGISTERS There are three registers required to hold the timer value. These three registers can be read at different cycles, It is recommended that the least significant byte be read first for the most accuracy. TABLE 71 SONGBASE Offset 03h POR Value Bit 7:4 R Name TMCOUNT2 (RW/RO) - MULTIMEDIA TIMER COUNT REGISTER 2 D7 R 0 R/W RO D6 R 0 D5 R 0 D4 R 0 0 Function Reserved. These bits return zeros. D3 D2 D1 D0
TMCOUNT2[7:0] 0 0 0
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Preliminary Specification
ThunderBird AvengerTM PCI Audio Accelerator
Bit 3:0 Name TMCOUNT2 R/W RW Function
SAA7785
High Nibble Timer Count. This nibble is the most significant digits of the timer value.
TABLE 72 SONGBASE Offset 02h POR Value Bit 7:0
TMCOUNT1 (RW) - MULTIMEDIA TIMER COUNT REGISTER 1 D7 D6 D5 D4 D3 D2 D1 D0
TMCOUNT1[7:0] 0 Name R/W RW 0 0 0 0 Function Middle Byte Timer Count. This byte is the middle significant digits of the timer value. 0 0 0
TMCOUNT1
TABLE 73 SONGBASE Offset 01h POR Value Bit 7:0
TMCOUNT0 (RW) - MULTIMEDIA TIMER COUNT REGISTER 0 D7 D6 D5 D4 D3 D2 D1 D0
TMCOUNT0[7:0] 0 Name R/W RW 0 0 0 0 Function Low Byte Timer Count. This byte is the least significant digits of the timer value. 0 0 0
TMCOUNT0
PCI I/O SPACE GPIO SUPPORT The Multimedia Timer house eight General Purpose I/O ports. These ports are independently controlled under host software. TABLE 74 SONGBASE Offset 04h POR Value Bit 7:0 Name PGPIO_DIR 0 R/W RW 0 0 PGPIODIR (RW) - PCI GENERAL PURPOSE INPUT/OUPUT DIRECTION D7 D6 D5 D4 D3 D2 D1 D0
PGPIO_DIR[7:0] 0 0 Function PCI General Purpose I/O Data Direction Bit. These bits control whether the GPIO pins 0 through 7 act as an input or an output. 0 = Selected GPIO pin is an output. 1 = Selected GPIO pin is an input. 0 0 0
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Preliminary specification
ThunderBird AvengerTM PCI Audio Accelerator
SAA7785
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1999 All rights reserved. Printed in U.S.A. Date of release: 11-99 Document order number: 9397-750-06592
Philips Semiconductors
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